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Single-loop sigma delta modulator design and verification for cognitive IoT applications

Vamsee Krishna S. (Jawaharlal Nehru Technological University, Anantapuramu, India)
Sudhakara Reddy P. (Srikalahasteeswara Institute of Technology, Srikalahasti, India)
Chandra Mohan Reddy S. (Jawaharlal Technological University, Anantapuramu, India)

International Journal of Pervasive Computing and Communications

ISSN: 1742-7371

Article publication date: 27 July 2020

Issue publication date: 21 July 2021




A third-order discrete time sigma delta modulator (SDM) is proposed with optimum performance by addressing instability and power dissipations issues, and a novel SDM architecture is designed and verified in behavioural modelling in MATLAB/SIMULINK environment. Simulation results show that performance parameters of proposed modulator achieved SNR of 105.41 dB, SNDR of 101.96 dB and DR of 17 bits for the signal bandwidth of 20 kHz.


This paper describes single-loop SDM design with optimum selection of integrator weights for physiological signal processing in IoT applications.


The proposed discrete time modulator designed with 1-bit quantizer and optimum oversampling ratio proved as power efficient. Integrator scaling coefficients are generated in LabVIEW environment for pure third-order noise shaping.


This paper contains the novelty in the work, and it is suitable for cognitive Internet of Things applications.



S., V.K., Reddy P., S. and Reddy S., C.M. (2021), "Single-loop sigma delta modulator design and verification for cognitive IoT applications", International Journal of Pervasive Computing and Communications, Vol. 17 No. 3, pp. 261-270.



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