Low power modular redundancy: a power efficient fault tolerant approach for digital circuits

Abstract

Purpose

To increase protection level against transient faults, circuit designers usually take advantage of redundant structures like Triple Modular Redundancy (TMR). Since redundancy compel a significant power overhead, proposing a low power fault tolerant technique in digital circuits is the main objective of this research work.

Design/methodology/approach

In order to moderate power consumption, we use a dual to triple modular redundancy. In fact, we put one of the modules in a TMR system in sleep mode while the other two operating modules are producing the same outputs. Once a mismatch is detected, the third one exits the sleep mode and the dual modular redundancy (DMR) approach turns into a conventional TMR. Also a novel stoppable clock generator is proposed to handle the sleep mode of the third module. Finally, a new three-input majority voter, compatible with our proposed technique, is presented.

Findings

Power analysis of combinational circuit benchmarks, ISCAS85, and ISCAS89 as sequential circuit benchmarks are depicted. Simulation results show the power reduction of up to 30% in comparison with the conventional modular redundancy approach.

Originality/value

Since modular redundancy is the most effective and the most well-known fault tolerant approach which is widely used in reliable circuits designs, it is important to reduce its power consumption. In this paper configuring the sleep mode operation of a circuit and stoppable clock generator lead to a new TMR technique in which the power consumption is strongly reduced.

Citation

Ansari, M.S., Mahani, A. and Mohammadi, K. (2016), "Low power modular redundancy: a power efficient fault tolerant approach for digital circuits", COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, Vol. 35 No. 3. https://doi.org/10.1108/COMPEL-08-2015-0266