In this short communication, transition times of input signals for various stages of a repeater‐chain loaded VLSI interconnects are studied.
It is observed that for a fixed number of repeaters a smaller load will reduce transition time. The effect is not very significant, if the load is moderate.
Method can be very useful for short‐circuit power estimation in repeater‐chains.
Chandel, R., Sarkar, S. and Agarwal, R. (2005), "Transition time considerations in repeater‐chains", Microelectronics International, Vol. 22 No. 3, pp. 39-40. https://doi.org/10.1108/13565360510610530Download as .RIS
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