Study of avalanche breakdown (MI) mode in sub micron MOSFET device

Abstract

Purpose

To study the breakdown (MI) mechanism in the sub‐micron MOSFET device.

Design/methodology/approach

Second‐order Poisson's differential equation is solved for suitable boundary condition to find the electric field expression for the sub‐micron devices. With the help of the electric field expression the exact relation for multiplication factor is derived, and then the equation for breakdown voltage has been generated.

Findings

This research paper provides the following findings: by controlling oxide thickness, junction depth and drain voltage, the breakdown can be easily controlled in the sub‐micron device; multiplication factor is not only affected by maximum field but also due to critical field; for very low gate voltage, the offset voltage mainly governs the breakdown; the breakdown voltage increases continuously as the channel length increases. It means, for larger channel length the breakdown will occur at high drain voltage.

Research limitation

This paper is based on the assumption that the electric field along the channel is independent of the junction depth (although not correct) and varying linearly from zero to E_sat.

Orginality/value

The paper derived the exact expression of the multiplication factor. Also discusses that for MI mode of breakdown, the breakdown voltage increases slowly with the gate voltage and approximated by drain saturation voltage plus offset voltage.

Citation

Singh, A.K. (2005), "Study of avalanche breakdown (MI) mode in sub micron MOSFET device", Microelectronics International, Vol. 22 No. 1, pp. 16-20. https://doi.org/10.1108/13565360510575503