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Ultra-thin chip packaging (UTCP) is one of the flexible assembly technologies, by which thinned dies are encapsulated inside spin-coated dielectric films. For sake of higher density integration and bending stress suppression, two UTCPs can be stacked vertically. The purpose of this paper is to present an improved UTCP process flow to embed thinned chip in a symmetric dielectric sandwich for a flat topography. The UTCP flat top surface is suitable for metallization and further 3D stacking.

In the new process, a central photosensitive polyimide film is introduced, in which a cavity is made for the embedded chip. The cavity is defined by lithography using the chip itself as a photo-mask. In this way, the cavity size and position is self-aligned to the chip. The chip thickness is compensated by the surrounding central layer, and a UTCP with flat topography (flat UTCP) is realized after top dielectric deposition.

A batch of daisy chain test vehicles was produced. The feasibility of the process flow is verified by optical and electrical measurements. The result shows 100 percent yield, which is much better than previous work. A thermal humidity test showed no significant degradation of the flat UTCPs after 1,000 hours.

High yield fabrication of flat UTCP is first shown. An innovative self-alignment lithography step is introduced to make a cavity in dielectric for chip thickness compensation by using the chip itself as a photo-mask.