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The increased use recently of area‐array technology in electronic packaging has similarly increased the importance of predicting the thermal distribution of area‐array solder interconnection. As the interconnection technology for flip chip package is getting finer and smaller, it is extremely difficult to obtain the accurate values of thermal stresses by direct experimental measurements. Different types of solder bumps used for interconnection would also influence the thermal distribution within the package. Because the solder balls are too small for direct measurement of their stresses, finite element method (FEM) was used for obtaining the stresses instead.

This paper will discuss the results of the thermal stress distribution using numerical method via ABAQUS software. The variation of the thermal stress distribution with the temperature gradient model was evaluated to study the effects of the different material thermal conductivity of solder bumps used. A detailed 2D finite element model was constructed to perform 2D plain strain elastoplastic analysis to predict areas of high stress.

It is found that thermal distribution of solder bumps starts to propagate from the top region to the bottom region of the solder balls. Other than that, thermal stress effect increases in parallel with the increasing of the temperature. The simulation results shows that leaded solder balls, SnPb have higher maximum thermal stress level compared to lead‐free SAC solder balls.

The paper describes combination of stress with thermal loading correlation on a flip chip model. The work also shows how the different thermal conductivity on solder balls influences the thermal induced stress on the flip chip package.