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The coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB) materials causes a reliability issue for ball grid array type electronic packages. This makes it difficult for conventional wafer level chip scaled packaging (WLCSP) with large die to satisfy the reliability requirements. Therefore, in this study a novel solder joint protection‐WLCSP (SJP‐WLCSP) structure is proposed to overcome the reliability issue.

The SJP‐WLCSP makes use of a delaminating layer to reduce the problem of CTE mismatch. In the SJP‐WLCSP, a delaminating layer is interposed between the top layer of the chip and the bottom insulating layer of the redistribution copper metal traces. As a result, the stress on the solder joints can be released by allowing cracks to form in the delaminating layer.

To elucidate the thermo‐mechanical behaviour of tin‐lead eutectic solder joints and copper traces, a non‐linear analysis, based on a 3D finite element (FE) model, under accelerated thermal test loadings was carried out. The maximum equivalent stress/strain in the solder joints predicted by the FE simulation were found to diminish significantly when applying the delaminating layer. In addition, parametric FE analysis was also applied in this study, and based on the design concepts within this study, a robust novel SJP‐WLCSP could be achieved.

In this work, a new packaging concept with high reliability, low cost and easy fabrication was developed to reduce the shear stress in the solder joints due to the CTE mismatch between silicon chips and organic PCBs.