3D Packaging Seminar TWI, Granta Park, Abington, Cambridge – 23 May 2012

Citation

Goosey, M. (2012), "3D Packaging Seminar TWI, Granta Park, Abington, Cambridge – 23 May 2012", Circuit World, Vol. 38 No. 3. https://doi.org/10.1108/cw.2012.21738caa.019

3D Packaging Seminar TWI, Granta Park, Abington, Cambridge – 23 May 2012

Article Type: Conferences and exhibitions From: Circuit World, Volume 38, Issue 3

On 23 May 2012 TWI hosted a seminar on 3D packaging at is conference centre in Granta Park, Abington, Cambridge. Organised by NMI with support from iMAPS and the Innovative Electronics Manufacturing Research Centre (IeMRC), this network event had the objective of presenting delegates with details of the latest technology roadmap developments, as well as information on the challenges and opportunities associated with 3D packaging.

The seminar began with an introduction and welcome by Paul Jarvie of NMI who thanked TWI for hosting the event and the IeMRC and iMAPS for providing additional support. He then introduced NMI, which was a trade body for electronics in the UK with over 220 members and whose activities encompassed all aspects related to semiconductor technology. Paul also highlighted NMI’s involvement in the “Electronic Systems – Challenges and Opportunities” (ESCO) Report (www.esco-report.com) and Power Electronics UK. He also referred the attendees to a “power electronics capability directory” which mapped the UK power electronics supply chain capability. Additionally, NMI was active in the Automotive Electronic Systems Network and supported the UK Electronics Skills Forum, which aimed to encourage the best talent to become involved in electronics and which was helping to address the diminishing skills capability in the UK. He concluded by giving a brief overview of the IeMRC funded FAMOBS project that was being led by Heriot Watt University.

The first technical presentation was then given by Andrew Richardson from Lancaster University, whose talk was entitled “Inside 3D Packaging Technology”. Andrew began by giving an overview of his packaging related work at Lancaster, which included engagement in multi-partner European projects around MEMS packaging. He then discussed the challenge of achieving best functionality without limiting performance in the context of integrating MEMS type devices. MEMS packaging had additional demands as it often required the interaction of the MEMS device with the environment. This meant that there was a need for more interfaces, which had to be addressed in terms of ensuring overall system reliability was achieved. He then covered the effects of packaging materials on the functional performance of MEMS type devices. Thermal expansion mismatches between different materials were a common cause of reliability problems and, in 3D packaging, the substrate was often part of the overall package. There were also many other integration challenges such as provision of interconnects, choice of materials, need for self-testing and self-monitoring and the design itself; design for X was crucial for future MNT integration. Andrew then gave an overview of some MEMS application areas and examples included pressure sensors, gas sensors, flow sensors, gyroscopes and optical sensors. He described the environmental challenges that had to be accommodated by electronics and illustrated the demands that had to be met in automotive applications. The market drivers for 3D packaging were then outlined. These included increased functionality per unit area, more I/Os and higher operating speeds. The packaging hierarchy was also described and this ranged from wafer level packaging through multichip modules up to system level packaging. The example of wafer level packaging was described in detail and its advantages and disadvantages were defined. WLP offered the advantages of being able to test at the wafer level, as well as small package size and weight, direct chip attachment to the wafer and improved electrical and mechanical performance. It was noted, however, that plastic encapsulation could cause stresses in the semiconductor substrates and related reliability problems. 3D packaging of semiconductor die into a package was typically described as an example of Level 1 packaging. Examples of work that had been done in this area were then given and Andrew referred to a project called “DAVID IST-027240”, which had down-scaled the assembly of vertically interconnected devices. This was an EC supported project and more information was publically available. Finally, Andrew stated that there was a packaging roadmap that contained a lot of useful information and this was available from Marc Desmulliez at Heriot Watt University.

Chris Rider from the Cambridge Integrated Knowledge Centre (CIKC) then covered the subject of “Integrating Large Area Electronics with Silicon – a new packaging challenge”. He began by outlining the activities of the CIKC in Cambridge related to large area electronics and this included the use of new functional materials in applications such as lighting, photovoltaics and flexible displays, etc. The best performance in this area was likely to come from the attachment of chips to flexible substrates. However, there were many challenges, not least of which was achieving reliability. There were many so-called “brand enhancement opportunity” applications for this type of technology. Interest was growing in attaching bare die to flexible substrates, but this currently had even more challenges, especially as flexibility often had to be maintained and the typical substrate materials used could not be heated to high temperatures, e.g. during die attachment. Chris was working on an EPSRC proposal to establish a Centre for Innovative Manufacturing in large area electronics. He encouraged those with an interest to contact him at: chris.rider@eng.cam.ac.uk

The next speaker was Per Viklund of Mentor Graphics who gave a presentation on “Advancements in 3D Packaging – pushing the limits of traditional EDA tools”. He began by outlining the evolution of IC packaging and covered routable substrates, flip chip die attachment, multi-device packages and through silicon vias. He then went on to describe the complexity of the off chip interconnect network across multiple dies and the need to optimise the design of the interconnects to give best signal flow and hence performance. Per stated that 3D stacking was not new in terms of packaging design and that the design tools had already been modified to support 3D. For some designs, the use of 2.5D interposers was a viable alternative and it offered a lower risk migration path towards a full 3D IC approach. These interposers could be both active and passive devices, the active interposers containing device layers as well as metal layers. The use of silicon interposers enabled TSVs to be moved off of the active die and also enabled the integration of passive devices. They were also compatible with older established wafer fabs. Per then outlined the tasks that had to be undertaken in terms of the physical design and modelling required to develop a silicon interposer. This was a particular challenge as pin counts for some overall package designs could be in the region of 100,000 or beyond. The real solution to this approach required a cross-domain, co-design methodology encompassing the die, package and board levels. He concluded by saying that here was a need to achieve an industry standard in interposer design and cross domain design tools were now required more than ever.

The final speaker in the morning session was Keith Strickland from Plessey Semiconductor and his presentation was called Packaging – an EPIC Story. He began by detailing the history of the Plessey Company and its current activities, which included manufacture of EPIC sensors, high brightness LEDs and smart lighting. The company’s core skill was in process technology. The focus of the presentation was on the EPIC sensor, which had been developed at the University of Sussex. EPIC was a highly sensitive electrometer that operated in both remote and contact modes. It had many uses including health and fitness applications and could be built into smart phones, sports watches and single arm ECG monitors. There were also applications in the automotive sector, as well as in toys and games. In all of these applications, reliability was very important. Another interesting application was in imaging the latent charge from fingerprints, which decayed with time. Keith then detailed the design of the EPIC sensor and the challenges in fabricating the device, especially in terms of integrating the sensor electrodes with the electronics. The packaging of the device was shown and a hybrid PCB based design had been evaluated along with a ceramic packaging approach. However, a QFN package was ultimately developed and the process flow was described. The EPIC product roadmap out to 2016 was then presented and this included a move to a 0.18 μm process, the introduction of low power versions along with the development of sensor arrays and micro-arrays.

After a lunch and networking break Alastair McGibbon gave a presentation on NMI’s R&D Policy Support. Alastair outlined how NMI worked with the funding holders in the UK to influence and support calls for proposals that would benefit the industry. NMI also helped with the transfer of know-how to build a presence around funding calls and to help partners to become involved. He then explained the many potential types of funding that were available and showed a funding map which highlighted the range of funding schemes at the regional, national and European levels. NMI were involved in the Advanced Manufacturing Supply Chain Initiative and it was seeking to encourage involvement from industry in this activity.

The second presentation of the afternoon session was given by Ollie Althorpe of ST Microelectronics Ltd and was on the subject of “Interconnect for 3D Technologies”. ST Micoelectronics was a large multinational organisation with 300 people and three R&D centres in the UK. Ollie stated that 3D packaging really came under the “More than Moore” category. He then described the use of through silicon vias in camera applications which, in the case of ST Microelectronics products, ranged from VGA to 24 megapixel devices. Unlike with normal silicon devices, where Moore’s law was a driver, for cameras, size reduction was constrained by the wavelength of light and the number of photons impinging per unit area. Therefore, alternative size reduction approaches were needed and the use of through silicon vias allowed the use of smaller outline packages with no pad extensions needed and an overall reduction in size. The use of TSVs also allowed the fabrication of camera modules that could be assembled via pick and place technology. Ollie then showed a series of schematics describing the processing steps for the camera modules. The company had shipped hundreds of millions of these devices and reliability had been very good. He concluded by stating that, in order to be successful, the whole process needed to be fully integrated and that one should only consider the use of 3D packaging approaches if no other viable routes were available!

The final presentation of the day was given by Martin Goosey, Industrial Director of the UK’s Innovative Electronics Manufacturing Research Centre (IeMRC). Martin’s presentation was entitled Technology Developments in 3D’. After giving an overview of the IeMRC and its packaging related research work, he described the current status and the likely progression in 3D packaging technology towards assembly at the wafer level and highlighted the benefits that 3D packaging could offer. He also detailed the issues associated with 3D packaging and then focussed on the challenges around thermal management in these highly integrated package types. In the final part of his presentation Martin described the possibility of using nanotechnology and nanomaterials as one way of overcoming the problems with heat and its dissipation in 3D packages. Materials such as carbon nanotubes and graphene had thermal conductivities of several thousand W/mK and, in theory at least, offered an order of magnitude improvement in thermal conductivity over more conventional materials such as aluminium nitride. Martin also explained that carbon nanotubes had been proposed as alternatives to copper in through silicon vias, where they offered the benefits of higher electrical and thermal conductivity along with a simpler deposition process. He concluded by outlining the IeMRC’s forthcoming events and invited attendees to attend them.

This was an excellent event that combined a wide range of varied and interesting presentations with a networking opportunity for the delegates. NMI are to be commended for organising such as successful event.

Martin Goosey23 May 2012