Valor introduces signal quality analysis technology into the next generation Enterprise 3000 DFM review system

Citation

(2000), "Valor introduces signal quality analysis technology into the next generation Enterprise 3000 DFM review system", Circuit World, Vol. 26 No. 1. https://doi.org/10.1108/cw.2000.21726aad.003

Valor introduces signal quality analysis technology into the next generation Enterprise 3000 DFM review system

Valor introduces signal quality analysis technology into the next generation Enterprise 3000 DFM review system

Keywords Valor, DFM

Valor Computerized Systems has announced the introduction of the Signal Quality Analyzer for the Enterprise 3000 DFM review system. Valor is the first company to address this issue and introduce signal quality analysis into the design for manufacturing review process. Hitherto, managing signal quality posed exponential challenges to the designer because of the lack of methods for verification.

The problem of signal quality analysis

Engineers and PCB designers currently rely on a methodology that represents a perfect case scenario for signal integrity modeling. Signal integrity calculations are made upstream during the early design stages, making assumptions about the physical board build, when no layout or physical model of the product exists. Later, when the PCB layout is complete, physical features may have been introduced which upset signal integrity and invalidate the original calculations. Examples of such occurrences are: clearances in ground planes below critical routes, pairs of critical routes running too close to each other or parallel with each other for too long a distance. Such problems result in malfunctioning prototype products and design revisions spins, damaging cost and time-to-market objectives.

Physical verification of signal quality design characteristics

With the Enterprise 3000, signal quality related analysis is performed by referencing the geometric locations of each signal to specific features and applying a sophisticated shape based algorithm. This technique confirms if the desired signal performance will in fact be achieved in the finished layout design.

It provides real measurements based on the physical design and pinpoints exact locations of the problem areas. The basis for the analysis is the ODB++ physical model of the printed circuit assembly, extracted directly from the PCB layout system database, which is then passed directly into manufacturing without further changes or processing.

For further information, please contact, Julian Coates, Valor Computerized Systems NV. Tel: +32 16 44 06 91; E-mail: julian@valor.com