EIPC Summer Conference, Luxembourg, 27-28 June 2013

Circuit World

ISSN: 0305-6120

Article publication date: 18 November 2013



(2013), "EIPC Summer Conference, Luxembourg, 27-28 June 2013", Circuit World, Vol. 39 No. 4. https://doi.org/10.1108/CW.21739daa.012



Emerald Group Publishing Limited

EIPC Summer Conference, Luxembourg, 27-28 June 2013

Article Type: Conferences and exhibitions From: Circuit World, Volume 39, Issue 4

PCB Differentiation Through Technology – Made in Europe

A small landlocked country in western Europe, bordered by Belgium, France, and Germany, Luxembourg covers an area of less than a thousand square miles and has a population of little more than half a million. The world’s only remaining grand duchy, with the world’s highest gross domestic product per capita, Luxembourg was the location for the 2013 Summer Conference of the European Institute of Printed Circuits.

Day 1 – June 27

EIPC Chairman Alun Morgan welcomed an international audience, with delegates from 12 countries, to a two-day event with a carefully chosen programme which included a keynote session, 16 technical papers and a visit to the factory of Circuit Foil. After announcing the launch of EIPC’s freshly designed web site: http://www.eipc.org, and inviting papers for the 2014 ECWC World Conference, http://www.ecwc13.org, Morgan introduced the Keynote presentation from Phil Plonski of Prismark Partners, who held the rapt attention of the audience with a fascinating discussion exploring the challenges and opportunities presented by new design trends and manufacturing technologies for PCBs.

He commented that the electronics industry was increasingly mature, with relatively anaemic growth trends and a constant demand for cost reduction. But traditional market segmentation disguised an important issue: the division between mature and growth segments. And in reality the growth segment still presented tremendous opportunities for complex, useful, cost-effective electronics, the principal drivers being high-functional portable devices, computing and communications infrastructure and the increasing functionality of automotive electronics. Virtually everything else fell into the classification of “mature technology”, which was where the opportunities had been in the past but where costs were now rapidly reducing. Current technology areas of interesting activity in PCB fabrication were flexibles, package substrates and microvia HDI.

“We take things apart!” Plonski declared, as he showed a series of tear-down cross-sections of current high-end mobile devices, revealing a spectacular array of features. “You find a lot of interesting technology when you micro-section things!” One of his examples was the Samsung EXYNOS 5410 system-on-a-chip processor, used in the Galaxy S4 smartphone, with an octa-core CPU package using 28 nm HKMG semiconductor technology, and a 2GB LPDDR3 memory package sat on top with flip-chip interconnection. The processor substrate was 2-2-2 microvia construction, 340 μm thick, with 25 μm lines and spaces and 75 μm vias. The whole lot was contained within a package 14.6 mm square and 1.1 mm thick, and interconnected to the PCB through 1,100 balls at 0.4 mm pitch. “It’s always exciting to see how the design community are packing more and more into the z-axis!”

In RF modules the trends were towards size reduction and the integration of multiple functions on the same die. Leading-edge RF module substrate technology was typically 1-2-1 microvia, 700 μm thick, with 70-80 μm lines and spaces and 60 μm vias.

There was increasing convergence of PCB assembly and semiconductor packaging techniques. The desire for true three-dimensional integration was driving the development of embedded component technologies, and advanced PCB fabrication, assembly and test processes were being exploited to deliver integrated modular functionality. Many of the individual steps were quite mature technologies, early applications were already in production and there were many enabling opportunities in prospect.

Plonski switched his focus to flexibles. Dismantling an iPad 3 had revealed 16 separate flexible and flex-rigid circuits. For example, the display-driver board was four-layer polyimide flex with six-layer HDI. There was plenty of evidence of the trend for flexibles fabricators to deliver pre-assembled modules, and also for modules to be capable of utilisation in multiple and diverse applications. “Think modular” was the message.

Turning his attention to the roadmap for flip-chip and CSP packaging, Plonski observed that the trend was to finer line rather than higher layer-count. Substrates with line widths of 20 μm or less and via diameters of 50 μm or less were already available in volume, and he had seen examples of 5 μm line and space full-additive from Japan. “Think small – this is not semiconductor technology, this is upcoming PCB technology!” he declared and showed a series of illustrations of imaginative design in medical and automotive applications. In many instances, the base technologies already existed, as did modules that could be integrated into functional devices at relatively low cost and high volume as a result of creative thinking.

His closing words were “There’s a whole lot of stuff going on that’s going to drive this industry forward […]”.

The second presentation in the keynote session came from Gordon Biezeveld, Business Manager with UL and based in The Netherlands. Quoting Henry Ford: “Obstacles are those frightful things you see when you take your eyes off the goal”, he set out to clarify the myths and mysteries surrounding the likely qualification changes associated with emerging requirements for FR4 laminates.

Stressing that the definition of “safety” was constantly evolving, he explained that complex issues of the present had replaced concerns of the past and that the safety landscape of tomorrow was yet to be defined. Looking specifically at FR4 laminates, the traditional material based on brominated epoxy resin had evolved in response to demands for improved thermal reliability and electrical performance, as well as international environmental directives, to a point where traditional and modified materials were no longer comparable from a testing point of view, and it was clear that some revised classifications were needed.

There had been real problems in getting industry bodies and standards authorities to agree on exact definitions. The 2011 JTPIA/JPCA proposal to classify all laminates with a 130°C relative thermal index, regardless of chemical composition, as FR4 did not reach consensus, neither did the 2012 UL proposal to categorise FR4 into groups based on chemistry and performance. But there had been agreement on the 2013 IPC proposal to classify FR4 into two groups based on flame retardant system, resulting in two new UL/ANSI designations: FR4.0 for brominated and FR4.1 for halogen-free materials.

What was the impact of this agreement on laminate manufacturers? In essence, traditional brominated FR4 s changed their designation to FR4.0 and no additional testing was needed, although file and listing cards would be updated to reflect the new nomenclature. But non-halogen materials, designated FR4.1, would require testing for halogen content according to the new paragraph 8.2 in UL 746E. Sample requirements were to be sent to UL by July 2013, and samples submitted for review by February 2014. An issue still to be resolved was that laminate manufacturers would be forced to revise all their technical data sheets and brochures for FR4 materials.

Solder resist manufacturers would not need to do additional testing on recognised FR4 laminates, but this would be limited to FR4.0 and new work requests would be required to follow the published UL 746E standard, with testing required for each ANSI requested.

Printed circuit manufacturers would not need new type designation or additional testing for their recognised PCBs on FR4 material, although file updates would be required after completion of laminate and solder resist file review. As for new work requests for PCBs using FR4.0 and FR4.1, the CCIL/MCIL and coatings programmes were OK and applied to the majority of FR4.0 materials, although some testing would be required for FR4.1. There were no CCIL/MCIL or coatings programmes in place for FR4 materials with blended resins. Full testing, including delamination and flammability would be necessary and a new type-designation was required.

Biezeveld acknowledged that end-product users accustomed to ordering FR4-based products would have a hard time understanding the changes, although he invited people to continue to have an open dialogue with UL and to give active input.

Session 1 of the technical programme was moderated by Jean-Claude Roth, Technical Manager at CCI Eurolam in France, whose first speaker was IPC Vice President of International Relations David Bergman, talking about standards and how they affect business. Reminding delegates that their customers were central to their businesses, Bergman explained that standards were a medium for communication. They helped to deliver products faster by not having to specify basic requirements for form, fit and function. Additionally, having standards reduced overall costs through use of a common understanding between users and suppliers, and increased the reproducibility of products and services.

Standards development was a major function of IPC, and Bergman described how the standardisation process worked. The Technical Activities Executive Committee, chaired by Doug Pauls, was the governing body for all standards development work within IPC and was composed of senior technical people from within the electronics manufacturing industry. Standards were developed through committee structures operating at national and international level. Bergman listed 22 separate committees, explaining that there were over 260 subcommittees and task groups, supported by a network of over 10,000 volunteers. The development of a consensus standard followed a logical process, of which the major steps were project initiation notification, project acceptance, working draft development, final draft for industry review, proposed standard for ballot, negative comment resolution and publication, with a typical timeline of up to 36 months start to finish. Participating companies were largely defence and aerospace related.

The most popular standards revolved around printed circuit board assembly, fabrication and design. The top five sellers all had certification programmes associated with them, and the uptake of certification programmes was at record levels. Bergman demonstrated the relevance and applicability of IPC standards and joint-industry standards at just about every stage of the printed circuit design, fabrication, assembly and test process. There were over 300 active standards in the IPC collection, and these were available in multiple languages – for example, standards had been requested in 15 different languages from Europe.

From the business of standards to the technology of filling small holes – Dr Maria Nikolova, Senior Research Fellow with MacDermid in the USA, described an improved copper plating process for filling microvias and through-hole vias.

Driven by demands for better performance, miniaturisation and price reduction of sequential build-up microvia high-density interconnect in portable electronics, techniques of via filling by copper electroplating had become popular, and several proprietary processes were available. But during the deposition of metal in the vias, a substantial thickness tended to be built up on the surface and this limited the ultimate fine-ness of conductor that could be etched. The objective was to formulate an electrolyte that would enable the efficient and reliable filling of blind holes whilst minimising surface deposition.

Dr Nikolova explained the function of the inorganic constituents of an acid copper plating electrolyte: copper metal, sulphuric acid and chloride, and then described how the organic wetter, brightener and leveller additives modified the structure and distribution of the deposited metal. MacDermid’s new formulation enabled shorter cycle times and faster filling than earlier chemistries, and gave significantly lower surface thickness. In the example illustrated, vias 100 μm diameter and 75 μm deep were filled in 40 min, with 9 μm at the surface, compared with typically 50 min and 14 μm from an established formulation.

Higher concentrations of copper sulphate had been observed to have a positive effect on hole filling, particularly at larger via diameters, whereas sulphuric acid and chloride concentrations had insignificant effect. Of the organic additives, leveller had the most significant effect, as might be expected, whereas beyond a certain concentration brightener had no effect and neither did wetter over a wide concentration range. Bath agitation was also a factor, and high flow rates contributed to dimple formation. All of the via sizes plated exhibited excellent thermal integrity under solder shock conditions. The deposits were bright and levelled, with a fine equiaxial grain structure. The development work had been extended to study the filling of photo-defined bumps and pillars for IC substrates and the filling of through-vias for three-dimensional chip-stacking applications, with encouraging results.

Spirit Circuits’ Technical Sales Manager Les Round has become a well-known spokesman on the technology and applications of insulated metal substrates (IMS). He described a new-generation material developed by Cambridge Nanotherm, where a nanocrystalline dielectric layer of aluminium oxide was formed in-situ on an aluminium base by an electrochemical deposition process. The dielectric was available in thicknesses of 10-30 μm, with a thermal conductivity of 7 W/mK.; the material could be used in applications where extremely low thermal impedance was demanded. Indeed its thermal impedance was less than half of that of the currently best available conventional IMS materials. Copper for circuit fabrication was either press-bonded to the dielectric as a resin-coated foil with 4-μm adhesive or, in a premium version of the material, deposited directly on the dielectric by an electroless plating process. These substrates were competitive in chip-on-board and chip-on-heatsink applications, and offered an alternative to alumina and aluminium nitride tiles.

Round described a practical comparison test conducted in front of a live audience at a recent LED workshop, where a series of “Star” PCBs on different IMS substrates were assembled with Cree XM-L high-performance LEDs and thermocouples for temperature monitoring. With the devices powered-up at 1,000 and 3,000 mA, those based on Nanotherm showed remarkably lower junction temperatures than those based on standard IMS substrates.

Final presentation of Session 1 came from Alfred Kaiserman, AOI and AOR Products Manager with Orbotech in Belgium, who described how users could make best use of the capability and functionality of their automated optical inspection and automated optical repair facilities without additional investment. For example, using an AOI system for checking for presence and position of holes, or detecting annular ring violations by intelligent drill rest-ring reporting. Even if the ring could not be clearly seen, its geometry was precisely calculated and violations were reported only if they contravened defined criteria, rather than be flagged as false alarms. Inclusions in base materials, which might not be detected in a conventional binary image, could be distinguished and reported by the latest image analysis algorithms, and the principle could be applied to the detection of copper shorts under solder mask, or contamination and discolouration of solder pads.

Thick copper had traditionally presented inspection problems to AOI systems, a specific example being the combination of 80 μm copper and white ceramic substrate used in automotive LED lighting. Enhanced-angle illumination and polarised light enabled effective image capture of the etched edges of thick copper tracks, in conjunction with advanced software to analyse the resulting data. Additionally, modern AOI systems could be used for the detection of laser drill defects, and for flex-rigid inspection.

An innovative application of automated optical repair systems was the repair of shorts covered by solder mask. A small window was opened in the solder mask to allow access for the short to be laser-ablated away, and the repair could then be spotted-in with solder mask.

It has become customary in recent years for EIPC conferences to include a visit to a manufacturing plant, and the Luxembourg event gave delegates the opportunity to observe the manufacturing process for copper foil at the factory of Circuit Foil Luxembourg SARL, a bus ride away in Wiltz.

Circuit Foil Customer Care and Group Quality Director Raymond Gales gave an introduction and overview of the operation, which each month converts 850 tons of copper into 3.5 million m2 of foil. In a highly automated process, copper metal is first dissolved in sulphuric acid, and the filtered and purified electrolyte is fed to a series of continuous plating machines. In each plating machine, the cathode is a large-diameter stainless steel cylinder, half-immersed in the electrolyte and continuously rotating at low speed. Copper is electrodeposited at high current density and the deposit is peeled off as a roll of continuous foil. The roll is later transferred to another continuous plating line for the bonding treatment to be applied, then trimmed to width and stored ready to be cut to sheets according to customer requirement. The product range includes standard HTE foils from 12 to 210 μm and a series of special-purpose foils: ultra-flat profile, ultra-thin and resin coated.

Delegates enjoyed a comprehensive guided tour of the plant followed by an evening reception, which brought the proceedings of the first day to a convivial conclusion.

Day 2 – June 28Advanced PCB Research Projects, PCB Design and Novel Technologies

A well-rested and bright-eyed audience re-assembled for an early start to the second day of the EIPC Summer Conference in Luxembourg and enjoyed an intense programme of 12 technical papers in three sessions: Advanced PCB Research Projects, PCB Design and Novel Technologies, with an apparent preponderance of professors in the presenters’ line-up.

EIPC Vice-President Technology Professor Martin Goosey opened the proceedings and moderated Session 2: Advanced PCB Research Projects, commenting that the Institute continued to actively support, engage and participate in collaborative projects. He introduced the first speaker, Professor John Tyrer from Loughborough University in the UK, whose presentation was entitled: “3-D printing of functional polyethylene structures with embedded circuit boards using novel holographic optics”.

“I like growing functional things!” Professor Tyrer declared as he described how laser direct writing could be used to produce real functional embedded circuits for security applications. Both the substrate and the conductor pattern were formed directly by laser-sintering of polymeric and metallic powders. Laser direct writing offered rapid prototyping capability by a high-speed layer-by-layer process that enabled complex structures to be created at high resolution. However, when plastic powders were sintered by conventional laser technology, there was a tendency for them to yield products with high porosity. The gaps between particles were not filled and heat was not transferred down to the lower layers of powder. This was a consequence of the Gaussian distribution of energy within a round laser beam giving non-uniform temperature distribution, leading to strong Marangoni flow, laser-induced thermal ejection, porosity resulting from local boiling of the material, thermal degradation in the region central to the beam, and thermal stresses due to uneven cooling.

The answer was to optimise the shape, intensity and focus of the laser beam to suit the characteristics of the material, and this was done using computer-generated holographic optical elements to reconstruct the beam intensity to a custom-designed profile. Professor Tyrer showed how circuits could be constructed from polyethylene powder and silver paste, using CO2 lasers with beam profiles separately optimised for each material. He also discussed the complex mathematics used to model the physics of the process, explained the curing mechanisms and the morphology of the sintered materials and showed the stages in the formation of an actual embedded circuit, an example of “playing with the laser beam and getting it to do the job you want it to.”

The SUSONENCE project, Sustainable Ultrasonically Enhanced Chemical Processes, in which EIPC had been directly involved as a consortium partner, was concerned with developing advanced sonochemical processes to reduce chemical usage and decrease waste in the PCB and metal finishing industries. Stuart Dalrymple, Project Manager at C-Tech Innovation in the UK, referred to traditional processes for surface modification using aggressive chemistries and process conditions: permanganate desmearing of PCBs, chromic acid etching of plastic moulding resins and hydrofluoric acid etching of ceramics and glass, and asked “Can sonochemistry help?”

Reviewing the principles of acoustic cavitation, microjetting and microstreaming in the frequency range 20-100 KHz, he indicated how these effects could potentially be exploited to physically abrade surfaces and break down chemical diffusion layers then gave some examples of actual experimental results on “Noryl” polyphenylene ether and ABS/polycarbonate resins, using ultrasound in water. He demonstrated the effects of ultrasonic frequency, ultrasonic intensity, probe-to-workpiece distance, water temperature and surfactant addition on weight loss. The project had produced a technology platform from which potential commercial applications were emerging and a TSB-funded feasibility study, carried out under the project name HEPROC, had investigated the effect of ultrasound on the permanganate etch process for drill smear removal in printed circuit fabrication. Using ultrasound, it had been possible to reduce permanganate concentration by 50 percent and temperature by 25°C and achieve the same results as the standard rocess in terms of weight loss and interconnection reliability. The next stage of the SUSONENCE project was a scale-up from laboratory to industrial implementation, and 300-litre evaluation units were currently being installed in PCB manufacturing plants.

So many acronyms! The next European project to be discussed was MESMOPROC Maskless Electrochemical Surface Modification. Professor Sudipta Roy of Royenface Ltd, a spin-out from Newcastle University in the UK, described how principles developed for an electrochemical micro-fabrication process called EnFACE were being scaled-up as a method for transferring circuit patterns onto PCB substrates. The process used a metallic tool with a resist pattern on its working surface, placed in close proximity to the substrate, and electrically connected through a plating rectifier. Electrolyte was pumped through the system to deliver fresh solution to the anode and cathode and to remove by-products. Depending on the polarity, metal was selectively plated on or etched from the substrate. The principal benefit of the EnFACE technique was that a single tool could be used for many patterning operations and hence offer cost savings by greatly reduce the requirement for photoresist and its associated processing.

Significant challenges remained to be addressed in engineering the process for industrial PCB fabrication, including implementing an agitation scheme to stir the electrolyte within the narrow gap between the tool and substrate, using this agitation scheme for larger substrates and achieving accurate registration between tool and substrate. Professor Roy discussed how the MESMOPROC partnership was addressing the issue of ensuring effective agitation within the tool-substrate gap to overcome the rapid depletion of metal ions during the electrodeposition of copper. Ultrasonic agitation methods were being studied as a means of controlling the diffusion layer and promoting mass transfer of copper ions, and a limiting current technique was being used to determine the effectiveness of agitation. An industrial-scale plating cell, incorporating ultrasonic agitation, had been designed and trials were proceeding. “Watch this space!”

The next presentation focused on another application of electrochemistry. Professor Dr Magda Lakatos-Varsanyi from BAY-Zoltan Ltd in Hungary discussed pulse-plated nano-structured iron layers for microelectronics applications. She explained that downscaling of power electronics devices had led to a demand for higher driving frequencies and higher working temperatures for inductive elements, and there was intensive research to find metallic-alloy replacements for commonly-used ferrites to allow higher flux densities and higher working temperatures, and to shift eddy-current frequency resistance limits above the 1 MHz region. For surface-mounted inductive elements, the natural choice was a thin-film magnetic material that could be prepared by electrodeposition. The soft magnetic properties could be improved by using pulsed electrodeposition to give a nano-crystalline structure, which could be tailored by electrolyte composition and pulse plating parameters.

Professor Lakatos-Varsanyi described her experimental methods and testing procedures in detail. The outcome was that excellent soft magnetic pure iron with 12 nm grain size could be deposited from an electrolyte containing ferrous chloride, ferrous sulphate and magnesium sulphate. The layers were textured and exhibited a flat hysteresis loop, with a frequency limit of 20 MHz at a layer thickness of 10 μm. Iron-nickel alloy layers deposited by pulse plating exhibited grain sizes of 5-8 nanometres and excellent soft magnetic properties, with low magnetic coercivity and low magnetic loss.

Session 3 of the conference was dedicated to PCB design, and was moderated by Oldrich Simek, owner of PragoBoard in the Czech Republic. His first two presenters were recognised specialists in high-speed design: Neil Chamberlain and Martyn Gaudion, from Polar Instruments in the UK.

Neil Chamberlain started from first principles in a discussion on design considerations for the routing of ultra-high-speed differential pairs, and the four critical signal integrity issues the designer needed to try to control were impedance, loss, cross-talk and mode conversion. “Impedance is about managing reflections”. Any mismatch in impedance would cause some of the signal power to be reflected back to its origin, rather than being carried all the way along the transmission line to the far end, and the ratio of energy bounced back depended on the impedance mismatch. Single-ended impedance mimicked the characteristics of a coaxial cable; differential impedance drove signals in equal and opposite directions, so that noise tended to be cancelled out, provided that the two lines were exactly the same.

To calculate impedance accurately required the use of a field solver, with trapezoidal modelling to properly represent the geometry of the conductor. And designers needed to be aware that solder mask could have a dramatic effect on the impedance of outer-layer tracks, particularly if it was hygroscopic. The limitations of materials were of fundamental significance in designing differential pairs and resin modelling was an important consideration. Typical FR4 laminate had a bulk dielectric constant of about 4.2, but there was a wide disparity between the individual values of glass (at about 6.0) and resin (at about 3.2). Thus, a conductor could experience local variations in dielectric constant depending on where it sat relative to the glass weave within the laminate. Some laminate manufacturers had gone to great lengths to minimise the effect by using “flat-glass” fabrics, but it still had to be recognised and taken into account.

Turning his attention to signal loss, Chamberlain acknowledged that signal lines were rarely ideal, and long lines and high speeds could contribute to loss by DC resistance. Of the characteristics most affecting loss, line length could only be controlled at the design stage, but dielectric loss could be controlled by appropriate material selection. Resistive copper loss could be controlled by conductor cross-sectional area and stack-up design, and loss due to copper surface roughness by choosing an appropriate grade of foil. He concluded that although loss and impedance were independent and required different measurement techniques, it was important to control both.

Martyn Gaudion led the discussion of loss into more detail, describing work he had done jointly with Intel to offer their designers the opportunity to accurately predict insertion loss on stripline traces and achieve cost-effectiveness and repeatability in the real-life situation where PCBs could be sourced from a wide range of different manufacturers. The study was carried out on SET2DIL coupons representing a variety of designs and materials, gathered from multiple sources, together with information regarding dielectric material, copper foil type and design geometries. Differential insertion loss, impedance and resistance measurements were made on the coupons, and samples were cross-sectioned to measure actual trace dimensions. The measurements were compared with results from modelling. The exercise had shown that, given adequate knowledge of the design, differential insertion loss could usually be predicted to within 0.05 dB per inch at 4 GHz, provided all the variables were known accurately.

Nikola Kontik, Business Development Manager with Zuken UK, took a look into new technology solutions and future challenges in PCB design. Apart from the inescapable trend to increased design complexity, two particular electronic product design challenges facing the PCB designer were the disconnect between product planning and product realisation, and the third-dimension problems presented by advances in packaging technology.

Time-to-market pressures were reducing design cycle time and changing the shape of concurrent design. Whereas separate design departments might previously have worked independently at PCB and system level, the present trend was to use a multi-level design platform that allowed teams to work concurrently on complex multi-board electronic designs and take a three-dimensional approach to optimising interconnectivity all the way down to the silicon.as well as collaborating closely with mechanical designers, so that the whole system was effectively designed as one. The coordination of global design teams, library and design data management and IP protection were additional issues to be considered.

What challenges did the future hold for the designer? On one hand, developments in internet-capable converging technologies and mobile electronic systems: tablets and ultrabooks, smartphones, smart televisions, smart grids and advanced metering infrastructures, and in the automotive area, developments in communication and wireless technology, in-car infotainment, web-browsing and online services, Bluetooth and near-field communication and wireless networks, intelligent systems, advanced driver assist systems, sensors and proximity controls. All to be designed with leading-edge technology…

Noted for his plain-talking approach to design issues, Martin Cotton, Director of Technology PCB Europe with Sanmina-SCI, began his presentation on practical design considerations of high speed PCBs with the statements: “I will be assuming that you know what the following are: impedance, resistance, jitter, frequency, etc. This is not a classroom for hardware designers – it’s not a classroom at all. The word I have chosen is Practical!”

Cotton had joined the PCB world 17 years ago, from a long-term background in electronic design, hoping to make a difference. “I failed! They still don’t listen. They still don’t talk to each other.”

The practical example he chose for illustration was a 36-layer backplane, 100 Ω impedance, working at a data rate of 10 Gb’s. He emphasised the distinction between data rate and frequency, and asked the question whether the data rate referred to a single differential pair channel or for a buss, because the buss speed was the total of all the channels in that buss. In his terminology, 100 Ω differential impedance used two tracks operating in harmony such that losses were kept to a minimum. The geometry of those tracks and their positioning with the PCB build structure were critical to realising a successful design and hence being able to manufacture at good yield. The setting-up of differential pairs began with material selection, and he recommended talking to material suppliers to get the benefit of their experience in designing materials with Dk and Df values to suit particular data rate and speed applications. Then it was necessary to create “cells”, defining trace separation, pair separation and layer-to-layer separation. He was not a fan of the old “3×separation” rule for establishing approximate cell geometrics, and preferred impedance modelling with specialist software for calculating dielectric separation.

Stack-up design began with a blank sheet, and needed to be finalised long before any conductor routing was contemplated. Trace mapping gave a guide to the understanding of the availability of space and the density of tracking practicable and depth-of-complexity was a way of measuring initial layer requirement. The cost could then be estimated and the actual layout started, with periodic checking simulations to ensure good signal integrity.

In Cotton’s actual example, once the layout was complete, post-layout simulation revealed signal integrity issue with 90 of the total of 2,000 differential pairs in the design. There were two options: fix them: by reviewing them individually, which would take time and effort, or by incorporating 6 additional layers, which would save time but significantly increase unit cost and have additional consequences on mechanical details. Cotton’s experience was that most design managers would never allow the time to fix the problem properly, but in this instance he had stood his ground and insisted the designer be given sufficient time to clean up all the differential pair conflicts and realise the original design objective and unit cost. “Spend the time up-front. Design once, make many times!”

Final session of the day, on a theme of novel technologies, was moderated by Pete Starkey, Technical Editor with I-Connect007.

The first presentation was in two parts. Dr Ulrich Prinz, from Enthone and Arne Schnoor from LPKF Laser and Electronics, both based in Germany, reviewed recent developments for plating laser direct structured serial parts and prototypes based on one-step copper technology.

Laser direct structuring techniques had become key to the successful manufacture of moulded interconnection devices, which were widely used in smartphones and tablets as antenna components. A significant part of the cost of these components was in the metallisation process, and Dr Prinz described an improvement in electroless copper deposition technology which offered significant cost reduction. A pre-seeded ABS was generally used for the antenna mouldings and because this was only weakly catalytic after laser structuring, a very active electroless copper strike-bath formulation was necessary to achieve satisfactory initial coverage before transferring the work into a more stable chemistry to build up the thickness to 15-20 μm. Because of its high activity, the strike bath was operating at the limit of its stability and needed to be changed frequently, incurring substantial disposal costs.

There had been two significant areas of process development: a more flexible electroless copper formulation, capable of single-step operation, and an activating process to increase the catalytic reactivity of the precursor particles compounded into the plastic. Upon laser structuring, although these particles were uncovered within the plastic matrix, they failed to be completely converted into catalytic sites. Immersing the laser-structured moulding in the activator chemistry substantially increased the conversion so that electroless plating was more efficiently initiated and the strike bath was no longer necessary. The technology could be adapted for plastics other than ABS. Higher bath loadings and shorter plating times were possible with the new electroless chemistry, and waste treatment and water consumption were substantially reduced.

A further innovation from LPKF, described by Arne Schnoor, was a laser-direct-structurable lacquer that could be applied to parts moulded from standard plastics for purposes of rapid prototyping. And this was complemented by a very simple-to-operate electroless copper chemistry, developed in cooperation with Enthone, which enabled the concept of an in-house “laboratory in a box” to be realised. As well as rapid prototyping, this self-contained package could be used for initial evaluation of laser parameter settings and laser-direct-structurable plastics development.

Professor Martin Goosey returned to the presenters’ table, this time in his role as a technical consultant with MTG Research in the UK, and gave a fascinating account of a novel use of waste natural products for metals recovery. It was estimated that the UK shell-fish industry dumped, legally or illegally, about 15,000 tons of crab shells annually. And it was known that the material of which crab shells are composed, chitin, has an affinity for heavy metals. Applying some lateral thinking, it was proposed to evaluate this waste material, which is expensive to dispose of legitimately, as a substitute for ion-exchange resin in the removal of copper from metal-finishing effluent. It was observed that crab shells had the ability to absorb 250 mg of copper per gram of shell, and to reduce the concentration of copper in solution down to the 0.1 ppm level. The activity of chitin could be increased by converting it to chitosan by a simple procedure of heating in sodium hydroxide solution. Once absorbed, it was found possible to desorb the copper into sulphuric acid and reclaim the metal by electroplating. A feasibility study had been completed, and further work was necessary to assess many variables and to optimise the chemistry.

Professor Goosey took the opportunity to review the FP7 ASPIS Project, in which EIPC is an active partner. Now in its final stages, the ASPIS Project had set out to investigate fundamental failure modes and mechanisms of ENIG coatings, to develop an ENIG screening tool, to develop improved coating methods and materials from both aqueous and ionic-liquid systems, and to verify the compatibility of the technology with assembly methods and practices. Up to date information was available on the web site: www.aspis-pcb.eu

Professor Jan Vanfleteren from the University of Ghent in Belgium demonstrated what could be achieved by the intelligent application of established PCB fabrication and assembly concepts and techniques to the development of stretchable circuits that could be straightforwardly transferred to industrial manufacture.

The fundamental requirements he defined were that the PCB processing and assembly should be done on a flat substrate, that standard off-the-shelf components should be used, and that the overall process should follow as closely as possible an industry-typical manufacturing route. In accordance with this concept, stretchable circuit designs consisted of a number of small rigid islands, each carrying a limited number of small components or a single large component, interconnected by meander-shaped copper conductors embedded in an elastic polymer. A lot of effort had gone into optimising the detail geometry of the meander pattern in order to maximise the mechanical reliability of conductors, particularly in the transition area between rigid and elastic elements, where a gradual transition in encapsulant thickness made an additional contribution to the durability of the interconnect.

Professor Vanfleteren described the manufacturing process for “stretchable moulded interconnect” (SMI). A temporary FR4 carrier was coated with a wax adhesive. Separately, a sheet of copper foil was coated with photo-definable polyimide, patterned to support the copper meanders and component islands. The two were bonded together and the copper was imaged and etched, solder mask applied to the component islands and components placed and reflow soldered with SAC alloy. The top side of the assembly was encapsulated by liquid injection moulding with a silicone or polyurethane elastic resin, then the temporary adhesive was melted to allow the assembly to be detached from the FR4 carrier and the second side was encapsulated by liquid injection moulding to give the finished SMI device.

Final presentation of the conference came from Raymond Gales, Customer Care and Group Quality Director with Circuit Foil. With reference to the conference theme of “differentiation through technology” he demonstrated how a European manufacturer of copper foil had responded to the requirements of the portable communications industry with ultra-thin peelable foils as an enabler for chip-scale packaging substrates. Build-up substrates for mobile CPUs were fabricated by techniques such as modified-semi-additive-process (MSAP) and coreless build-up.

Conventional subtractive technology was limited by etching capability, and could not achieve the ultra-fine line widths demanded for chip-scale packaging. Semi-additive techniques offered a solution, provided a base foil was available that was thin enough to be flash-etched. Also, substrates clad with ultra-thin foil with a low-reflectance surface were suitable for direct CO2 laser drilling and provided a means of achieving high-end buried and blind via interconnectivity through sequential build-up. Coreless technologies in package substrates were developing to satisfy the increasing demand for smaller, lighter devices with superior electrical performance. Gales explained in detail how Circuit Foil had established a customised range of peelable ultra-thin foils with functional thicknesses down to 2 μm, with carefully controlled characteristics to enable direct laser drilling and the realisation of 30 μm lines and spaces by modified semi-additive processing.

Alun Morgan brought the proceedings to a close, with special thanks to the companies who had sponsored the event, and acknowledged the contributions of the speakers and the attention of the delegates.

EIPC events consistently promote the high-level exchange of knowledge, experience and opinion, both in the formal sessions and in the many informal discussions outside the conference room. The Summer Conference was a great success, and a great credit to the behind-the-scenes work of the EIPC staff for their faultless and seamless organisation, administration and management of the event.

Pete Starkey

June 2013

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