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This paper sets out to propose a wafer prealigner based on multi‐sensor integration and an effective prealignment method implemented on it.

The wafer and notch eccentricities, on which wafer prealignment is based, are calculated with the peripheral data of the wafer detected by a laser displacement sensor and a transmission laser sensor by means of barycenter acquiring algorithm in a one‐particle system.

The center and notch prealignment precisions of the system are, respectively, ±1.5 μm and ±30 μrad. Experimentation has proved the validity and effectiveness of the system.

The wafer prealigner is a subsystem of the lithography in the semiconductor industry. The prealignment algorithm can be implemented in any object with random figures.

The periphery of the wafer is detected by a high‐precision laser displacement sensor and a low‐cost transmission laser sensor instead of a CCD linear sensor used by traditional wafer prealigners, which saves the space occupation of the structure and enhances the systematic prealignment precision. Using barycenter acquiring algorithm in a one‐particle system to calculate the wafer and notch eccentricities is effective and valid.

The aim of this study is to make a contribution towards reducing the deflections of silicon wafers. The deformation of silicon wafers used in the manufacture of electronic micro-components is one of the most common problems encountered by industrialists during manufacturing. Stack warping is typically produced during the process of depositing thin layers on a substrate. This is due to the thermal-mechanical stresses caused by the difference between the thermal expansion coefficients of the materials. Reducing wafer deformation is essential to increase reliability and improve quality. In this paper, the authors propose an approach based on minimal geometrical modifications to reduce the deformation of a silicon wafer coated with two thin layers. Numerical finite element models have been developed to evaluate the impact of geometrical modifications on warping amplitude. Finite element models have been validated compared with experimental models. The results obtained are encouraging and clearly show a considerable reduction in wafer deformation.

Reducing wafer deformation is essential to increase reliability and improve quality. In this paper, the authors propose an approach based on minimal geometrical modifications to reduce the deformation of a silicon wafer coated with two thin layers. Numerical finite element models have been developed to evaluate the impact of geometrical modifications on warping amplitude. Finite element models have been validated compared with experimental models.

The results obtained are encouraging and clearly show a considerable reduction in wafer deformation.

This paper describes the influence of geometric modification on wafer deformation. The work show also the cruciality of stress reduction in the purpose to obtain less wafer deformation.

Lapping is a vital flattening process to improve the quality of processed semiconductor wafers such as single-crystal sapphire wafers. This study aims to optimise the lapping process of the fixed-abrasive lapping plate of sapphire wafers with good overall performance [i.e. high material removal rate (MRR), small surface roughness (Ra) of the wafers after lapping and small lapping plate wear ratio (η)].

The influence of process parameters such as lapping time, abrasive size, abrasive concentration, lapping pressure and lapping speed on MRR, Ra and η of lapping-processed sapphire wafers was studied, and the results were combined with experimental data to establish a regression model. The multi-evaluation index optimisation problem was transformed into a single-index optimisation problem via an entropy method and the grey relational analysis (GRA) to comprehensively evaluate the performance of each parameter.

The results revealed that lapping time, abrasive size, abrasive concentration, lapping pressure and lapping speed had different influence degrees on MRR, Ra and η. Among these parameters, lapping time, lapping speed and abrasive size had the most significant effects on MRR, Ra and η, and the established regression equations predicted the response values of MRR, Ra and η to be 99.56%, 99.51% and 93.88% and the relative errors between the predicted and actual measured values were <12%, respectively. With increased lapping time, MRR, Ra and η gradually decreased. With increased abrasive size, MRR increased nearly linearly, whereas Ra and η initially decreased but subsequently increased. With an increase in abrasive concentration, MRR, Ra and η initially increased but subsequently decreased. With increased lapping pressure, MRR and η increased nearly linearly and continuously, whereas Ra decreased nearly linearly and continuously. With increased lapping speed, Ra initially decreased sharply but subsequently increased gradually, whereas η initially increased sharply but subsequently decreased gradually; however, the change in MRR was not significant. Comparing the optimised results obtained via the analysis of influence law, the parameters optimised via the entropy method and GRA were used to obtain sapphire wafers lapping with an MRR of 4.26 µm/min, Ra of 0.141 µm and η of 25.08, and the lapping effect was significantly improved.

Therefore, GRA can provide new ideas for ultra-precision processing and process optimisation of semiconductor materials such as sapphire wafers.

Wafer bonding is a key process for 3 D advanced packaging of integrated circuits. It requires very high accuracy for the wafer alignment. To solve the problems of large movement stroke, position calibration error and low production efficiency in optical alignment, this paper aims to propose a new wafer magnetic alignment technology (MAT) which is based on tunnel magneto resistance effect. MAT can realize micro distance alignment and reduces the design and manufacturing difficulty of wafer bonding equipment.

The current methods and existing problems of wafer optical alignment are introduced, and the mechanism and realization process of wafer magnetic alignment are proposed. Micro magnetic column (MMC) marks are designed on the wafer by the semiconductor manufacturing process. The mathematical model of the space magnetic field of the MMC is established, and the magnetic field distribution of the MMC alignment is numerically simulated and visualized. The relationship between the alignment accuracy and the MMC diameter, MMC remanence, MMC thickness and sensor measurement height was studied.

The simulation analysis shows that the overlapping double MMCs can align the wafer with accuracy within 1 µm and can control the bonding distance within the micrometer range to improve the alignment efficiency.

Magnetic alignment technology provides a new idea for wafer bonding alignment, which is expected to improve the accuracy and efficiency of wafer bonding.

Wafer transfer robots play a significant role in IC manufacturing industry and the end effector is an important component of the robots. The purpose of this paper is to improve transfer efficiency of a wafer transfer robot through study of its end effector, and at the same time to reduce wafer deformation.

Finite element method is adopted to analyze wafer deformation. For wafer transfer robot working in vacuum, for the first time, the authors apply the research of microfiber arrays inspired by gecko to the design of robot's end effector, and present equations between robot's transit acceleration and parameters of microfiber arrays. Based on these studies, a kind of micro‐array bump is designed and fixed to a structure optimized end effector. For wafer transfer robot working in atmospheric environment, the authors have analyzed the effects of different factors on wafer deformation. The pressure distributions in absorption area and calculation formula of maximal transfer acceleration are put forward. Finally, a new kind of end effector for atmospheric robot is designed according to these studies.

The experiments results show that transfer efficiency of wafer transfer robot has been significantly improved through application of the research in this paper. Also wafer deformation under absorption force has been controlled.

Through experiments it can be seen that the research in this paper can be used to improve robot transfer ability and decrease wafer deformation in the production environment. Also the studies of end effector lay a solid foundation for further improvement.

This is the first application of the research of gecko‐inspired microfiber arrays to vacuum wafer transfer robot. This paper also carefully analyzes effects of different factors on wafer deformation through finite element method.

This paper aims to review recent advances and applications of abrasive processes for microelectronics fabrications.

More than 80 patents and journal and conference articles published recently are reviewed. The topics covered are chemical mechanical polishing (CMP) for semiconductor devices, key/additional process conditions for CMP, and polishing and grinding for microelectronics fabrications and fan-out wafer level packages (FOWLPs).

Many reviewed articles reported advanced CMP for semiconductor device fabrications and innovative research studies on CMP slurry and abrasives. The surface finish, sub-surface damage and the strength of wafers are important issues. The defects on wafer surfaces induced by grinding/polishing would affect the stability of diced ultra-thin chips. Fracture strengths of wafers are dependent on the damage structure induced during dicing or grinding. Different thinning processes can reduce or enhance the fracture strength of wafers. In the FOWLP technology, grinding or CMP is conducted at several key steps. Challenges come from back-grinding and the wafer warpage. As the Si chips of the over-molded FOWLPs are very thin, wafer grinding becomes critical. The strength of the FOWLPs is significantly affected by grinding.

This paper attempts to provide an introduction to recent developments and the trends in abrasive processes for microelectronics manufacturing. With the references provided, readers may explore more deeply by reading the original articles. Original suggestions for future research work are also provided.

In wafer fabrication, the material cost of wafer is expensive. It is imperative to repair the defective wafers produced during the manufacturing process for reducing the cost and increasing the yield of wafer fabrication. However, repairing defective wafer will not only increase the work‐in‐process (WIP) level but the flow time of rework lots as well. In wafer fabrication, rework of wafer is only allowed in the photolithography area, where is the bottleneck of the entire wafer fab. The purpose of this paper is to develop a dispatching rule concerned with rework for photolithography area.

The research developed a load‐oriented integrated rule, Re‐Disp, to consider the lots' sequencing decision and rework consideration at the photolithography area, in wafer fabrication. Simulation test and statistical analysis have been done on a virtual wafer fabrication plant. In the simulation model, some combinations of dispatching and rework rules, which are popular in practice, have been modeled for benchmarking.

Integrated rules, Re‐Disp, is better than those combinations of dispatching rules and rework rules under statistical analysis. System will be more stable when the integrated dispatching rule is used for control of the wafer schedule.

The paper developed a new dispatching rule for wafer fabrication concerned with rework for photolithography.

The purpose of this paper is to characterize pressure non‐uniformity in a wafer‐to‐wafer bond chamber using pressure sensitive paper.

Pressure non‐uniformity in a wafer‐to‐wafer bond chamber is characterized using pressure sensitive paper. The effect of poor pressure uniformity is discussed, and the non‐uniformity corrected for use in a eutectic Au/Sn based wafer‐to‐wafer bond.

Several types of under solder metallization were also investigated, with Nb/Au seed metal providing the best overall result with good solder compression, liquid proof seal and minimal solder spill‐out. Solder compression versus pressure applied was studied to achieve an excellent gap control (2‐3 μm) between the bonded substrates.

This paper shows that characterization of applied pressure measured directly at the substrate is an important aspect in the development of high yielding bond processes.

The aim of this paper is to provide a new wafer prealigning robot for the photo‐etching facility during the manufacturing of IC products.

The shape center is measured by a reflection‐style laser sensor in the wafer's radial direction, and the position is measured by a penetration‐style laser sensor. A dynamic error compensation is applied to eliminate the radial runout and wobble of the rotary stage, which have effects on the measurement of the wafer's shape center.

It is found that the new wafer prealigning robot can satisfy the accuracy requirement.

The robot requires that the shape center can be accurately calculated.

The robot is applicable to wafer prealigning for the photo‐etching facility.

A wafer prealigning robot based on the shape center calculation method has been developed and is described in the paper.

The detection of invisible micro cracks (μ‐cracks) in multi‐crystalline silicon (mc‐si) solar wafers is difficult because of the wafers' heterogeneously textured backgrounds. The difficulty is twofold. First, invisible μ‐cracks must be visualized to imaging devices. Second, an image processing sequence capable of extracting μ‐cracks from the captured images must be developed. The purpose of this paper is to reveal invisible μ‐cracks that lie beneath the surface of mc‐si solar wafers.

To solve the problems, the authors first set up a near infrared (NIR) imaging system to capture images of interior μ‐cracks. After being able to see the invisible μ‐cracks, a region‐growing flaw detection algorithm was then developed to extract μ‐cracks from the captured images.

The experimental results showed that the proposed μ‐cracks inspection system is effective in detecting μ‐cracks. In addition, the system can also be used for the inspection of silicon solar wafers for stain, pinhole, inclusion and macro cracks. The overall accuracy of the defect detection system is 99.85 percent.

At present, the developed prototype system can detect μ‐crack down to 13.4 μm. The inspection resolution is high but the speed is low. However, the limitation on inspection speed can easily be lifted by choosing a higher resolution NIR camera.

Generally, this paper is a great reference for researchers who are interested in developing automatic optical inspection systems for inspecting solar wafer for invisible μ‐cracks.

The research described in this paper makes a step toward developing an effective while low‐cost approach for revealing invisible μ‐crack of mc‐si solar wafers. The advantages provided by the proposed system include excellent crack detection sensitivity, capability of detecting hidden subsurface μ‐cracks, and low cost.