Search results

Wafer transfer robots play a significant role in IC manufacturing industry and the end effector is an important component of the robots. The purpose of this paper is to improve transfer efficiency of a wafer transfer robot through study of its end effector, and at the same time to reduce wafer deformation.

Finite element method is adopted to analyze wafer deformation. For wafer transfer robot working in vacuum, for the first time, the authors apply the research of microfiber arrays inspired by gecko to the design of robot's end effector, and present equations between robot's transit acceleration and parameters of microfiber arrays. Based on these studies, a kind of micro‐array bump is designed and fixed to a structure optimized end effector. For wafer transfer robot working in atmospheric environment, the authors have analyzed the effects of different factors on wafer deformation. The pressure distributions in absorption area and calculation formula of maximal transfer acceleration are put forward. Finally, a new kind of end effector for atmospheric robot is designed according to these studies.

The experiments results show that transfer efficiency of wafer transfer robot has been significantly improved through application of the research in this paper. Also wafer deformation under absorption force has been controlled.

Through experiments it can be seen that the research in this paper can be used to improve robot transfer ability and decrease wafer deformation in the production environment. Also the studies of end effector lay a solid foundation for further improvement.

This is the first application of the research of gecko‐inspired microfiber arrays to vacuum wafer transfer robot. This paper also carefully analyzes effects of different factors on wafer deformation through finite element method.

The aim of this study is to make a contribution towards reducing the deflections of silicon wafers. The deformation of silicon wafers used in the manufacture of electronic micro-components is one of the most common problems encountered by industrialists during manufacturing. Stack warping is typically produced during the process of depositing thin layers on a substrate. This is due to the thermal-mechanical stresses caused by the difference between the thermal expansion coefficients of the materials. Reducing wafer deformation is essential to increase reliability and improve quality. In this paper, the authors propose an approach based on minimal geometrical modifications to reduce the deformation of a silicon wafer coated with two thin layers. Numerical finite element models have been developed to evaluate the impact of geometrical modifications on warping amplitude. Finite element models have been validated compared with experimental models. The results obtained are encouraging and clearly show a considerable reduction in wafer deformation.

Reducing wafer deformation is essential to increase reliability and improve quality. In this paper, the authors propose an approach based on minimal geometrical modifications to reduce the deformation of a silicon wafer coated with two thin layers. Numerical finite element models have been developed to evaluate the impact of geometrical modifications on warping amplitude. Finite element models have been validated compared with experimental models.

The results obtained are encouraging and clearly show a considerable reduction in wafer deformation.

This paper describes the influence of geometric modification on wafer deformation. The work show also the cruciality of stress reduction in the purpose to obtain less wafer deformation.

Varied shapes and sizes of different products with irregular rough surface and fragile properties give a challenge to traditional contact gripping. Single Bernoulli grippers are not suited to handle fragile objects as the impact of center negative pressure force could result in large deformation and stress which damage the materials, and they are also have some limitations for gripping objects with different large and small shapes. Thus, this paper aims to design a non-contact gripper for soft, rough-surfaced and fragile objects gripping with multi Bernoulli heads, which have optimal structures and parameters.

The compressed air is ejected into four Bernoulli heads through radial and long flow channels, then passes through four strip-shaped narrow gaps after fully developing in the annular cavity to provide negative pressure. Based on the mathematic model and the computational model, the key structural parameters affecting the gripping performance are selected, and parameters optimization of the gripper is performed by computational fluid dynamics simulation analysis and performance evaluation. The orthogonal method is used and L16 orthogonal array is selected for experimental design and optimization. The characteristics of the designed gripper are tested from the aspects of pressure distribution and lifting force.

From the applications in gripping different objects, the designed non-contact gripper can grip varied shapes and sizes of soft, rough-surfaced, fragile and sliced objects with little effect of torque.

In this paper, a non-contact gripper is designed for handling soft, rough-surfaced and fragile objects based on the Bernoulli principle. A systematic approach, which consists of modeling, simulation, optimization and measurement is provided for the non-contact gripper design and tests.

The purpose of this paper was to attempt to confirm the root cause of wafer damage issue by heavy Al wire wedge bonding and propose some permanent solutions for it.

The infra red–optical beam-induced resistance change (IR-OBIRCH) analysis defines the position of an abnormal hotspot. A cross section and an scanning electron microscope (SEM) confirmed the wafer damage issue and its position. Based on the position of wafer damage, the wedge tool with different life and Al buildup was checked found to be on the wedge tool. Finite element analysis (FEA) modeling analysis and simulation experiment guarantee the Al buildup, and low wedge deformation thickness (WDT) can cause the wafer damage issue. Finally, design of experiment (DOE) experiments are designed to optimize wedge tool dimension and wedge-bond parameters to eliminate wafer damage issue.

Wafer damage issue caused the Vpwr-OUTPUT leakage issue by IR-OBIRCH analysis. Al buildup was found on wedge tool with different life and its size gets larger along with the increase in wedge tool life. Low WDT and bigger Al buildup can cause the wafer damage. Designing new wedge tool and parameters optimization can increase WDT.

Because of the limitation of time and resources, finite element method (FEM) modeling and wedge tool dimension could not be studied more deeply.

This paper sets an example on how to find out the root cause of wafer damage by a step-by-step analysis and put forward a quick solution accordingly for the issue.

Wafer-level stencil printing of a type-6 Pb-free SAC solder paste was statistically evaluated at 200 and 150 μm pitch using three different stencil manufacturing technologies: laser cutting, DC electroforming and micro-engineered electroforming. This investigation looks at stencil differences in printability, pitch resolution, maximum achievable bump height, print co-planarity, paste release efficiency, and cleaning frequency. The paper aims to discuss these issues.

In this paper, the authors present a statistical evaluation of the impact of stencil technology on type-6 tin-silver-copper paste printing. The authors concentrate on performances at 200 and 150 μm pitch of full array patterns. Key evaluated criteria include achievable reflowed bump heights, deposit co-planarity, paste release efficiency, and frequency of stencil cleaning. Box plots were used to graphically view print performance over a range of aperture sizes for the three stencil types.

Fabrication technologies significantly affect print performance where the micro-engineered electroformed stencil produced the highest bump deposits and the lowest bump height deviation. Second in performance was the conventional electroformed, followed by the laser-cut stencil. Comparisons between the first and fifth consecutive print demonstrated no need for stencil cleaning in the case for the micro-engineered stencil for all but the smallest spacings between apertures. High paste transfer efficiencies, i.e. above 85 per cent, were achieved with the micro-engineered stencil using low aperture area ratios of 0.5.

Stencil technology influences the maximum reflowed solder bump heights achievable, and bump co-planarity. To date, no statistical analysis comparing the impact of stencil technology for wafer-level bumping has been carried out for pitches of 200 μm and below. This paper gives new insight into how stencil technology impacts the print performance for fine pitch stencil printing. The volume of data collected for this investigation enabled detailed insight into the limitations of the printing process and as a result for suitable design guidelines to be developed. The finding also shows that the accepted industry guidelines on stencil design developed by the surface mount industry can be broken if the correct stencil technology is selected, thereby increasing the potential application areas of stencil printing.

Structures play a very important role in developing pressure sensors with good sensitivity and linearity, as they undergo deformation to the input pressure and function as the primary sensing element of the sensor. To achieve high sensitivity, thinner diaphragms are required; however, excessively thin diaphragms may induce large deflection and instability, leading to the unfavorable performances of a sensor in terms of linearity and repeatability. Thereby, importance is given to the development of innovative structures that offer good linearity and sensitivity. This paper aims to investigate the sensitivity of a bossed diaphragm coupled fixed guided beam three-dimensional (3D) structure for pressure sensor applications.

The proposed sensor comprises of mainly two sensing elements: the first being the 3D mechanical structure made of bulk silicon consisting of boss square diaphragm along with a fixed guided beam landing on to its center, forming the primary sensing element, and the diffused piezoresistors, which form the secondary sensing element, are embedded in the tensile and compression regions of the fixed guided beam. This micro mechanical 3 D structure is packaged for applying input pressure to the bottom of boss diaphragm. The sensor without pressure load has no deflection of the diaphragm; hence, no strain is observed on the fixed guided beam and also there is no change in the output voltage. When an input pressure P is applied through the pressure port, there is a deformation in the diaphragm causing a deflection, which displaces the mass and the fixed guided beam vertically, causing strain on the fixed guided beam, with tensile strain toward the guided end and compressive strain toward the fixed end of the close magnitudes. The geometrical dimensions of the structure, such as the diaphragm, boss and fixed guided beam, are optimized for linearity and maximum strain for an applied input pressure range of 0 to 10 bar. The structure is also analyzed analytically, numerically and experimentally, and the results are compared.

The structure offers equal magnitudes of tensile and compressive stresses on the surface of the fixed guided beam. It also offers good linearity and sensitivity. The analytical, simulation and experimental studies of this sensor are introduced and the results correlate with each other. Customized process steps are followed wherein two silicon-on-insulator (SOI) wafers are fusion bonded together, with SOI-1 wafer used to realize the diaphragm along with the boss and SOI-2 wafer to realize the fixed guided beam, leading to formation of a 3D structure. The geometrical dimensions of the structure, such as the diaphragm, boss and fixed guided beam, are optimized for linearity and maximum strain for an applied input pressure range of 0 to10 bar.

This paper presents a unique and compact 3D micro-mechanical structure pressure sensor with a rigid center square diaphragm (boss diaphragm) and a fixed guided beam landing at its center, with diffused piezoresistors embedded in the tensile and compression regions of the fixed guided beam. A total of six masks were involved to realize and fabricate the 3D structure and the sensor, which is presumed to be the first of its kind in the fabrication of MEMS-based piezoresistive pressure sensor.

Ball‐bumping is a flexible low cost bumping technology based on the conventional wire bonding procedure. It is applicable to single chips or whole wafers as well as to substrates. As established wire‐bonding machines can be used, expensive bumping‐process equipment for phototooling and plating is not necessary. Flip‐chip bonding is the most advantageous attach method of high frequency applications. Compared with wire‐bonding and TAB it allows the highest contact density, the shortest signal paths and lowest interconnection parasitics. The reduced pad sizes and pitches, not only of GaAs devices, demand a well controlled bump deformation during flip‐chip bonding. This work develops process parameters for the flip‐chip bonding of silicon and GaAs devices with respect to the best interconnection result by lowest bonding force and ball‐bump deformation. Ball‐bumps with diameters of 50 and 80 urn (2.0 and 3.2 mils) were created using 98% AuPd bump wire with diameters of 18 µm (0.7 mil) and 25 µm (1.0 mil) respectively. Ball‐bumping with a minimal pitch of 70 µm (2.8 mils) has been achieved. A special preparation allowed the shear test investigation of each bump/pad interface after flip‐chip attach. Bonding forces of 20 and 25 cN/bump respectively lead to a good welding in the bump/substrate interface due to the special shape of ball‐bumps. For silicon devices which have a pad metallisation of aluminium, the shear forces of the bump/pad interface increase after flip‐chip bonding, too. No cratering of GaAs and silicon occurs after flip‐chip bonding due to a low bonding force ramp of 5 cN/s and 10 cN/s respectively. The flip‐chip attach of a Fujitsu FLR 016 GaAs‐FET which has pad sizes of 35 urn is demonstrated. In this case, substrate bumping is the more advantageous bumping method. The feasibility of fine‐pitch TAB attach using ball‐bumps is introduced. 100 µm (3.9 mils) pitch silicon devices with 328 pads were ball‐bumped for both solder and thermal‐compression TAB. Bond forces were in the range of 9–11 cN/bump and 15–21 cN/bump respectively. Pull forces of approximately 30 cN/lead show good results of the bump/lead interconnection after TAB.

This paper aims to investigate the changes in tensile properties of novel functionally graded materials (FGMs) and wafer structures created by direct metal deposition (DMD) additive manufacturing (AM) technology.

Laser-assisted DMD was used to create two innovative sets of metallic structures – the functionally graded and wafer-layered structures – using pairs of six different engineering alloys in different combinations. These alloys were selected due to their high popularity within a diverse range of industries and engineering applications. The laser-assisted DMD was selected as a suitable technique to create these complex structures because of its capability to deposit more than one alloy powder at a time. After creation of these structures, their tensile strength was tested in a series of tensile tests and the results were compared with those of single alloy samples.

It was observed that the mechanical properties of FGMs and wafer structure samples were clearly different from those of the single alloy samples, a fact which creates a whole pool of opportunities for development of new materials or structures with desired mechanical properties that cannot be achieved in single alloy parts.

The study demonstrates the application of the DMD process to produce unique structures and materials, which would be high in demand in engineering applications, where metallic parts are exposed to high loads and where excessive tensile stresses may adversely affect the performance of such parts.

This study aims to investigate the several parameters in wafer-level packaging (WLP) to find the most critical factor impacting the thermal fatigue life, such as the height of copper post, the height of solder bump, the thickness of chip. The FEA results indicate the height of solder bumps is the most important factor in the whole structure.

The copper post bumps with 65 µm pitch are proposed to investigate the thermal-mechanical performance of WLP. The thermal cycle simulation is used to evaluate the reliability of WLP by using finite element analysis (FEA). Taguchi method is adopted to obtain the sensitivity of parameters of three-dimension finite element model, for an optimized configuration.

It can be found that the optimal design has increased thermal fatigue life by 147% compared with the original one.

It is concluded that the finite element simulation results show outstanding thermal-mechanical performances of the proposed 65 µm pitch copper post bumps of WLP, including low plastic strain, high thermal fatigue life, which are desired for mobile device.

This paper aims to review recent advances and applications of abrasive processes for microelectronics fabrications.

More than 80 patents and journal and conference articles published recently are reviewed. The topics covered are chemical mechanical polishing (CMP) for semiconductor devices, key/additional process conditions for CMP, and polishing and grinding for microelectronics fabrications and fan-out wafer level packages (FOWLPs).

Many reviewed articles reported advanced CMP for semiconductor device fabrications and innovative research studies on CMP slurry and abrasives. The surface finish, sub-surface damage and the strength of wafers are important issues. The defects on wafer surfaces induced by grinding/polishing would affect the stability of diced ultra-thin chips. Fracture strengths of wafers are dependent on the damage structure induced during dicing or grinding. Different thinning processes can reduce or enhance the fracture strength of wafers. In the FOWLP technology, grinding or CMP is conducted at several key steps. Challenges come from back-grinding and the wafer warpage. As the Si chips of the over-molded FOWLPs are very thin, wafer grinding becomes critical. The strength of the FOWLPs is significantly affected by grinding.

This paper attempts to provide an introduction to recent developments and the trends in abrasive processes for microelectronics manufacturing. With the references provided, readers may explore more deeply by reading the original articles. Original suggestions for future research work are also provided.