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At present, over 95 percent of the manufactured packages are still being wire bonded. Owing to the ongoing trend of miniaturization, material changes, and cost reduction, wire bond‐related failures are becoming increasingly important. This paper aims to understand these kinds of failures.

Different finite element (FE) techniques are explored to their ability to describe the thermo‐mechanical behavior of the wire embedded in the electronic package. The developed nonlinear and parametric FE models are able to predict the strong nonlinear behavior of wire failures and multi‐failure mode interaction accurately and efficiently.

It is found that both processing and testing environments as well as the occurrence of delamination strongly increase the risk for wire failures. The results indicate that processing and testing influences are much less than those of the delamination.

Package designers should focus on limiting the occurrence of delamination around wire bond and/or stitch areas.

Combining the strengths of predictive modeling with simulation‐based optimization methods, the optimal wire shape is obtained.

The purpose of the present study was to review the thermo-mechanical challenges of reflowed lead-free solder joints in surface mount components (SMCs). The topics of the review include challenges in modelling of the reflow soldering process, optimization and the future challenges in the reflow soldering process. Besides, the numerical approach of lead-free solder reliability is also discussed.

Lead-free reflow soldering is one of the most significant processes in the development of surface mount technology, especially toward the miniaturization of the advanced SMCs package. The challenges lead to more complex thermal responses when the PCB assembly passes through the reflow oven. The virtual modelling tools facilitate the modelling and simulation of the lead-free reflow process, which provide more data and clear visualization on the particular process.

With the growing trend of computer power and software capability, the multidisciplinary simulation, such as the temperature and thermal stress of lead-free SMCs, under the influenced of a specific process atmosphere can be provided. A simulation modelling technique for the thermal response and flow field prediction of a reflow process is cost-effective and has greatly helped the engineer to eliminate guesswork. Besides, simulated-based optimization methods of the reflow process have gained popularity because of them being economical and have reduced time-consumption, and these provide more information compared to the experimental hardware. The advantages and disadvantages of the simulation modelling in the reflow soldering process are also briefly discussed.

This literature review provides the engineers and researchers with a profound understanding of the thermo-mechanical challenges of reflowed lead-free solder joints in SMCs and the challenges of simulation modelling in the reflow process.

The unique challenges in solder joint reliability, and direction of future research in reflow process were identified to clarify the solutions to solve lead-free reliability issues in the electronics manufacturing industry.

The purpose of this paper is to review recent advances in wire bonding of low‐k devices.

Dozens of journal and conference articles published in 2005‐2008 are reviewed.

The paper finds that many articles have discussed and analysed problems/challenges such as bond pad metal peeling/lift, non‐sticking on pad, decreased bonding strength and lower wire‐bond assembly yield. The paper discusses the articles' solutions to the problems and recent findings/developments in wire bonding of low‐k devices.

Because of the page limitation, only brief discussions are given in this paper. Further reading is needed for more details.

The paper attempts to provide an introduction to recent developments and the trends in wire bonding of low‐k devices. With the references provided, readers may explore more deeply by reading the original articles.

The purpose of this paper is to study the thermal warpage of a plastic ball grid array (PBGA) mounted on a printed circuit board (PCB) during the reflow process.

A thermal-mechanical coupling method that used finite-element method software (ANSYS 13.1) was performed. Meanwhile, a shadow moiré apparatus (TherMoiré PS200) combined with a heating platform was used for the experimental measurement of the warpage of PBGA according to the JEDEC Standard.

The authors found that the temperature profiles taken from the simulated results and experimental measurement are consistent with each other, only with a little and acceptable difference in the maximum temperatures. Furthermore, the maximum warpage measurements during the reflow process are 0.157 mm and 0.149 mm for simulation and experimental measurements, respectively, with a small 5.37 per cent difference. The experimental measurement and simulated results are well correlated. Based on the validated finite element model, two factors, namely, the thickness and dimension of PCB, are explored about their effect on the thermal warpage of PBGA mounted on PCB during the reflow process.

The paper provides a thorough parametrical study of the thermal warpage of PBGA mounted on PCB during the reflow process.

The findings in this paper illustrate methods of warpage study by combination of thermal-mechanical finite element simulation and experimental measurement, which can provide good guidelines of the PCB design in the perspective of thermal warpage during the reflow process.

The purpose of this paper is to review recent advances in fine and ultra‐fine pitch wire bonding.

Dozens of journal and conference articles published recently are reviewed.

The problems/challenges such as possible wire sweep and decreased bonding strength due to small wire sizes, non‐sticking, metal pad peeling, narrow process windows, wire open and short tail defects are analysed. The solutions to the problems and recent findings/developments in fine and ultra‐fine pitch wire bonding are discussed.

Because of the page limitation, only brief discussions are given in this paper. Further reading is needed for more details.

This paper attempts to provide an introduction to recent developments and the trends in fine and ultra‐fine pitch wire bonding. With the references provided, readers may explore more deeply by reading the original articles.

The flexible printed circuit board (FPCB) can be an alternative to the rigid printed circuit board because of its excellent flexibility, twistability, and light weight. Using FPCB to construct personal computer (PC) motherboard is still rare. Therefore, the present study aims to investigate the fluid‐structure interaction (FSI) behaviors of the newly proposed FPCB motherboard under fan‐flow condition in the PC casings.

The deflection and stress induced, which are usually ignored in the traditional rigid motherboard, are the main concern in the current FPCB motherboard studies. Only a few studies have been conducted on the effect of inlet locations, effect of inlet sizes, effect of multi‐inlets, and effect of a two‐fan system. These numerical analyses are performed using the fluid flow solver FLUENT and the structural solver ABAQUS; they are real‐time online coupled by Mesh‐based Parallel Code Coupling Interface (MpCCI).

A smaller inlet size can cause higher deflection and stress fluctuations, but the fluctuations can be reduced by incorporating the multi‐inlets design. In addition, the inlet locations and two‐fan system can prominently affect the magnitudes of the deflection and stress induced.

The current study provides better understanding and allows designers to be aware of the FSI phenomenon when dealing with the FPCB motherboard. Although the present study primarily focuses on the motherboard, the findings could also contribute valuable information for other FPCB applications.

The present study extends the FSI investigation from the previous novel approach of FPCB motherboard, and uniquely explores the behaviors of the FPCB motherboard inside different PC casings.

This paper attempts to review recent advances in wire bonding using copper wire.

Dozens of journal and conference articles published recently are reviewed.

The problems/challenges such as wire open and short tail defects, poor bondability for stitch/wedge bonds, oxidation of Cu wire, strain‐hardening effects, and stiff wire on weak support structures are briefly analysed. The solutions to the problems and recent findings/developments in wire bonding using copper wire are discussed.

Because of page limitation of the paper, only a brief review is conducted. Further reading is needed for more details.

This paper attempts to provide introduction to recent developments and the trends in wire bonding using copper wire. With the references provided, readers may explore more deeply by reading the original articles.

The purpose of this paper is to provide a design and material selection guideline for a plastic ball grid array (PBGA) package in order to improve its reliability and manufacturing ability after post mold cure.

Numerical experiments based on a three‐dimensional (3‐D) viscoelastic finite element method have been conducted to evaluate governing damage mechanisms after post mold cure (PMC) for PBGA packages. The parametric studies for the PBGA package with various molding compounds have been performed. A wide range of the modulus (1MPa∼15GPa) and the coefficient of thermal expansion (CTE) (10ppm∼300ppm) are evaluated to see feasibility of a new class of material set in the molding compound. Effects of thermo‐mechanical properties of selected molding compound on the warpage and residual stress of the PBGA are analyzed.

The present study shows that the material properties such as modulus and CTE of molding compounds play an important role in warpages and reliability of PBGA packages. After post mold cure, compressive normal stress σ_xx is observed in the silicon die, while tensile stress occurs in the rest of the PBGA package. The maximum normal stress σ_xx is observed at the center of the silicon die and decreases near the edge of the package. As the coefficient of thermal expansion of the silicon die is substantially less than that of the molding compound or substrate, the molding compound and the substrate are trying to shrink more when temperature decreases and in turn compressing the silicon chip. The molding compound with low modulus produces low stresses in the Si die and the die attach. Moreover, for the low modulus case, the CTE of molding compound does not affect the warpage of the PBGA package and the stresses in the silicon die or the die attach. However, for the high modulus case, the warpage and stresses are increased significantly by increasing the CTE of molding compound.

It is suggested that adhesion strengths of die attaches should be studied in future studies, since those affect the delamination between dies and substrates.

The findings can be used as general design guidelines for a PBGA package.

The results presented in the paper will be very useful to designers of PBGAs.

Integration of Cu/low‐k interconnects into the next‐generation integrated circuit chips, particularly for devices below the 90 nm technology node, has proved necessary to meet the urgent requirements of reducing RC time delay and low power consumption. Accordingly, establishment of feasible and robust packaging technology solutions in relation to the structural design, as well as material selection of the packaging components, has become increasingly important. Moreover, the nature of low‐k materials and the use of lead‐free solder greatly increases the complications in terms of ensuring enhanced packaging level reliability. The foregoing urgent issue needs to be quickly resolved while developing various advanced packages. This paper aims to focus on the issues.

The prediction model, especially for the fatigue life of lead‐free solder joints, combined with virtual design of experiment with factorial analysis was used to obtain the sensitivity information of selecting geometry/material parameters in the proposed low‐k flip‐chip (FC) package. Moreover, a three‐dimensional non‐linear strip finite element model associated with the two levels of specified boundary condition of global‐local technique was adopted to shorten the time of numerical calculation, as well as to give a highly accurate solution.

The results of thermal cycling in experimental testing show good agreement with the simulated analysis. In addition, the sensitivity of analysis indicates that the type of underfill material has a significant effect on the lead‐free solder joint reliability.

A suitable combination of concerned designed factors is suggested in this research to enhance the reliability of low‐k FC packaging with Pb‐free solder joints.