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The purpose of this paper is to investigate the impact of different distribution of shoot through mode on Z‐source inverter efficiency and particularly on complexity of switching pattern generation. Switching pattern generation has been optimized for field‐oriented control (FOC) of induction motor operating beyond its nominal speed which can be easily accomplished due to the input voltage boosting implemented inherently by Z‐source inverter. The proposed drive is unaffected to supply voltage sags, too.

The space vector modulation switching pattern of the traditional FOC drive was modified in order to insert shoot through mode necessary for input voltage boosting. Since this can be accomplished only on account of zero mode of the inverter, the active modes have to be reduced. Consequently, the output voltage space vector has to be reduced, as well.

In order to maximize profit of the input DC voltage and to omit the output voltage distortion, mathematical limitations have been derived giving the optimal boost ratio for required output voltage and ride‐through capability during voltage sags.

The experimental tests of upgraded FOC of induction motor with the proposed distribution of shoot through mode in the switching pattern of Z‐source inverter and optimized control of inverter voltage are demonstrated. It is also shown that such a drive can withstand a long period of input voltage sags and operate in a broader field weakening regime.

The paper's value lies in the overall, DSP‐based control of the induction motor supplied with Z‐source inverter gaining the maximum utilization of the input DC supply source and optimum trade‐off between inverter efficiency and inverter components voltage stress.

Multilevel inverters play a major role in the development of high-power industrial applications. In traditional low-level inverters (e.g. 2-level), the switching frequency is restricted and the harmonic spectrum of the system is hard to meet power requirements. Similarly, high-level inverters consist of a large number of switches, complex modulation techniques and complex hardware architecture, which results in high power loss and a significant amount of harmonic distortion. Furthermore, it is a must to ensure that every switch experiences the same stress of voltage and current. The purpose of this paper is to present an inverter topology with lower conduction and switching losses via reduced number of switches and equal voltage source-sharing technique.

Herein, the authors present a cascaded multilevel inverter having less power switches, a simple modulation technique and an equal voltage source-sharing phenomenon implementation.

The modulation technique becomes more complex when equal voltage source-sharing is to be implemented. In this study, a novel topology for the multilevel inverter with fewer switches, novel modulation technique, equal voltage source-sharing and Inductor-Capacitor-Inductor filter implementation is demonstrated to the reduce harmonic spectrum and power losses of the proposed system.

The nine-level inverter design is validated using software simulations and hardware prototype testing; the power losses of the proposed inverter design are elaborated and compared with the traditional approach.

Multilevel inverter (MLI) is an established design approach for inverter applications in medium-voltage and high-voltage range of applications. An asymmetric design synthesizes multiple DC input voltage sources of unequal magnitudes to generate a high-quality staircase sinewave comprising a large number of steps or levels. However, the implications of using sources of unequal magnitudes results in the requirements of a large variety of inverter switches and higher magnitudes of the total blocking voltage (TBV) rating of the inverter, which increase the cost. The purpose of this study is to present a solution based on algorithms for establishing DC source magnitudes and other design parameters.

The approach used in this study is to develop algorithms that bring an asymmetric cascaded MLI (ACMLI) design close to symmetric design. This approach then reduces the variety of switch ratings and minimizes the TBV of the inverter. Thus, the benefits of both asymmetric design (generation of a large number of voltage levels in the output waveform) and symmetric design (modularity) are achieved. The proposed algorithms can be applied to a number of ACMLI topologies, including classical cascaded H-bridge (CHB). The effectiveness of the proposed algorithms is validated by simulation in Matlab-Simulink and experimental setup.

Two new algorithms are proposed that reduce the number of variety of switches to just three. The variety can further be reduced to two under a specified condition. The algorithms are compared with the existing ones, and the results are promising in minimizing the TBV rating of the inverter, which results in cost reduction as well. For a specific case of four CHBs, the proposed Algorithm-1 produced 27% and Algorithm-2 produced 53% higher levels. Moreover, the presented algorithms produced minimum values of the TBV and resulted in minimum cost of inverter.

The proposed algorithms are novel in structure and have achieved the targeted values of minimized switch variety and reduced TBV ratings. Due to less variety, the inverter achieves a near symmetric design, which enables to attain the added advantages of modularity and reduced difference of power sharing among the DC sources.

These implementations not only generate excessive voltage levels to enhance the quality of power but also include a detailed investigating of the various modulation methods and control schemes for multilevel inverter (MLI) topologies. Reduced harmonic modulation technology is used to produce 11-level output voltage with the production of renewable energy applications. The simulation is done in the MATLAB/Simulink for 11-level symmetric MLI and is correlated with the conventional inverter design.

This paper is focused on investigating the different types of asymmetric, symmetric and hybrid topologies and control methods used for the modular multilevel inverter (MMI) operation. Classical MLI configurations are affected by performance issues such as poor power quality, uneconomic structure and low efficiency.

The variations in both carrier and reference signals and their performance are analyzed for the proposed inverter topologies. The simulation result compares unipolar and bipolar pulse-width modulation (PWM) techniques with total harmonic distortion (THD) results. The solar-fed 11-level MMI is controlled using various modulation strategies, which are connected to marine emergency lighting loads. Various modulation techniques are used to control the solar-fed 11-level MMI, which is connected to marine emergency lighting loads. The entire hardware system is controlled by using SPARTAN 3A field programmable gate array (FPGA) board and the least harmonics are obtained by improving the power quality.

The simulation result compares unipolar and bipolar PWM techniques with THD results. Various modulation techniques are used to control the solar-fed 11-level MMI, which is connected to marine emergency lighting loads. The entire hardware system is controlled by a SPARTAN 3A field programmable gate array (FPGA) board, and the power quality is improved to achieve the lowest harmonics possible.

The purpose of this paper is to present the three phase seven-level Z-source neutral point clamped (NPC) inverter with multicarrier pulse-width modulation (PWM) technique. Despite numerous topologies and modulation methods, there is a dire need of developing PWM techniques that can be deployed in multilevel inverters. These inverters decrease the total harmonic distortion and it has a good performance for various electrical power system applications. The proposed inverter is investigated for its performance by executing it in shoot through and non-shoot through modes.

The purpose is validated through MATLAB/Simulink software platform for implementing the proposed seven-level Z-source NPC inverter outlined with multicarrier based phase disposition technique. The experimental results are verified using SPARTAN 3E FPGA controller with the same control strategy.

The efficiency of the proposed inverter is confirmed in terms of increased and faster conversion in the shoot-through mode. By using PDPWM technique the maximum boost gain is achieved with lower modulation index. High control of DC voltage is obtained with only one DC voltage source and one Z network.

Three phase multilevel inverters are widely used in improving the output voltage quality and reducing the encountered electromagnetic interference in electronic device or circuitry. They are employed in medium and high –power applications to attain increased power ratings while decreasing the switching losses. The performance results shown in this paper will satisfy the above needs of usage in certain applications and less switching losses.

This paper aims to present an inverter with a current-source input for 400 Hz avionic systems to have a system which removes DC-link capacitors and presents a high efficiency.

A battery-powered DC link inductor generates a constant-current source. A single high-frequency switch is used to provide a sinusoidally modulated current before the inverter. The output of the switch is “unfolded” by a thyristor-based H-bridge inverter to generate an AC output current. The system uses a CL low-pass filter to obtain a 400 Hz pure sine wave by removing pulse width modulation components.

Simulations and Typhoon HIL real-time experiments were performed with closed-loop control to validate the proposed inverter concept while meeting the critical standards of MIL-STD-704F.

This current source inverter topology is suitable for avionic systems that require 400 Hz output frequency. The topology uses small DC-link inductor and eliminates bulky capacitor which determines the inverter lifetime.

The purpose of this paper is to present the Switched Inductor Z-Source Inverter (SLZSI) topology for three-phase on-line uninterruptible power supply (UPS) by employing third harmonic injected maximum constant boost pulse width modulation (PWM) control. Conventional UPS consists of step-up transformer or boost chopper along with voltage source inverter (VSI) which reduces the efficiency and increases energy conversion cost. The proposed three-phase UPS by using SLZSI has the voltage boost capability through shoot through zero state which is not available in traditional VSI and current source inverter.

Performance of three-phase on-line UPS based on ZLZSI by using third harmonic injected maximum constant boost PWM control is analyzed and evaluated in MATLAB/Simulink software and the results are compared with Z-source inverter (ZSI) fed UPS. Experimental results are presented for the validation of the simulation and theoretical analysis.

The output voltages, currents, THD values, voltage stress and efficiencies for different loading condition are determined and compared with the theoretical values and UPS with ZSI. The experimental results validate the theoretical and simulation results.

Compared with the traditional ZSI, the SLZSI provides high-voltage boost inversion ability with a very short shoot through zero state. This proposed UPS by using SLZSI increases the efficiency with less number of components, reduces the harmonics, increases the voltage gain and reduces the voltage stress.

Multilevel inverters become very popular in medium voltage applications owing to their inherent capability of reconciling stepped voltage waveform with reduced harmonic distortion and electromagnetic interference. They have several disadvantages like more number of switching devices required and devices with high voltage blocking and need additional dc sources count to engender particular voltage. So this paper aims to propose a novel tri-source symmetric cascaded multilevel inverter topology with reduced number of switching components and dc sources.

A novel multilevel inverter has been suggested in this study, offering minimal switch count in the conduction channel for the desired voltage level under symmetric and asymmetric configurations. This novel topology is optimized to prompt enormous output voltage levels by employing constant power switches count and/or dc sources of voltage. The topology claims its advantages in generating higher voltage levels with lesser number of voltage sources, gate drivers and dc voltage sources.

The consummation of the proposed arrangement is verified in Matlab/Simulink R2015b, and an experimental prototype for 7-level, 13-level, 21-level, 29-level, 25-level and 49-level operation modes is constructed to validate the simulation results.

The proposed topology operated with six new algorithms for asymmetrical configuration to propel increased number of voltage levels with reduced power components.

Multi‐level diode‐clamped inverters have the challenge of capacitor voltage balancing when the number of DC‐link capacitors is three or more. On the other hand, asymmetrical DC‐link voltage sources have been applied to increase the number of voltage levels without increasing the number of switches. The purpose of this paper is to show that an appropriate multi‐output DC‐DC converter can resolve the problem of capacitor voltage balancing and utilize the asymmetrical DC‐link voltages advantages.

A family of multi‐output DC‐DC converters is presented in this paper. The application of these converters is to convert the output voltage of a photovoltaic (PV) panel to regulate DC‐link voltages of an asymmetrical four‐level diode‐clamped inverter utilized for domestic applications. To verify the versatility of the presented topology, simulations have been directed for different situations and results are presented. Some related experiments have been developed to examine the capabilities of the proposed converters.

The three‐output voltage‐sharing converters presented in this paper have been mathematically analysed and proven to be appropriate to improve the quality of the residential application of PV by means of four‐level asymmetrical diode‐clamped inverter supplying highly resistive loads.

This paper shows that an appropriate multi‐output DC‐DC converter can resolve the problem of capacitor voltage balancing and utilize the asymmetrical DC‐link voltages advantages and that there is a possibility of operation at high‐modulation index despite reference voltage magnitude and power factor variations.

The purpose of this paper is to design a cascaded Multilevel inverter with reduce number of switches for high power applications. This paper came up with an innovative three-phase multilevel inverter (MLI) topology, which is a cascaded structure based on classical three-legged voltage source inverter (VSI) bridges as an individual module. The prominent advantage of this topology is that it requires only one direct current (DC) link system. The main characteristic of it is that a higher number of voltage levels can be achieved with considerably a smaller number of semiconductor switches, which improves the reliability, power quality, cost and size of the system significantly.

The individual modules are cascaded through three-phase transformers to provide higher voltage at the output with the higher number of voltage levels. In this work, the phase-shifted pulse width modulation technique is implemented to verify the result.

The proposed topology is compared with three-phase cascaded H-bridge MLI (CHB-MLI) and a modified CHB-MLI topology and found better in many aspects. The proposed MLI can produce a higher number of voltage levels with fewer semiconductor switches and associated triggering circuitry. As the device count in the proposed MLI is less compared to other MLI discussed, it tends to have less switching and conduction loss which increases the efficiency and reliability. As the number of level increases, the voltage profile and the total harmonic distortion of the proposed MLI improves.

This is a transformer-based modular cascaded MLI, which is based on classical VSI bridges. Here in this topology, a single module provides all three phases. So, a single string of cascaded modules is enough for three-phase multilevel voltage generation.