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The design of space-efficient support hardware for built-in self-testing (BIST) is of immense significance in the synthesis of present day very large-scale integration (VLSI) circuits and systems, particularly in the context of design paradigm shift from system-on-board to system-on-chip (SOC). This paper presents an overview of the general problem of designing zero-aliasing or aliasing-free space compression hardware in relation to embedded cores-based SOC for single stuck-line faults in particular, extending the well-known concepts of conventional switching theory, and of incompatibility relation to generate maximal compatibility classes (MCCs) utilizing graph theory concepts, based on optimal generalized sequence mergeability, as developed by the authors in earlier works. The paper briefly presents the mathematical basis of selection criteria for merger of an optimal number of outputs of the module under test (MUT) for realizing maximum compaction ratio in the design, along with extensive simulation results on International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits, with simulation programs ATALANTA, FSIM, and COMPACTEST.

Realizing aliasing-free space compressor for built-in self-testing of very large scale integration circuits and systems is of immense practical significance, especially due to the design paradigm shift in recent years from system-on-board to system-on-chip. This paper explores and provides new results on extending the scope of a recently developed approach to synthesizing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults. For a pair of response outputs of the circuit under test, the method uses the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input AND/NAND nonlinear logic. The process is illustrated with development details of space compressors for the International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits (results on full-scan sequential circuits though not included in the paper) using simulation programs ATALANTA and FSIM, showing the relevance of the technique from the viewpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thereby making it an ideal choice in actual design environments.