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The purpose of this paper is to explore a new possibility of providing high-temperature stable lead-free interconnections for low-temperature co-fired ceramics (LTCC) hotplate. For gas-sensing application, a temperature range of 200°C-400°C is usually required by the sensing film to detect different gases which imply the requirement of thermally stable interconnects. To observe the effect of parameters influencing power of the device, electro-thermal simulation of LTCC hotplate is also presented. Simulated LTCC hotplate is fabricated using the LTCC technology.

The proposed task is to fabricate LTCC hotplate with interconnects through vertical access. Dedicated via-holes generated on the LTCC hotplate are used to provide the interconnections. These interconnections are based on adherence and bonding mechanism between LTCC and thick film. COMSOL software is used for finite element method (FEM) simulation of the LTCC hotplate structure.

Thermal reliability of these interconnections is tested by continuous operation of hotplate at 350°C for 175 h and cycling durability test performed at 500°C. Additionally, vibration test is also carried out for the hotplate with no damage observed in the interconnections. An optimized firing profile to reproduce these interconnections along with the experimental flowchart is presented.

Research activity includes design and fabrication of LTCC hotplate with metal to thick-film based interconnections through vertical access. Research work on interconnections based on adherence of LTCC and thick film is limited.

A new way of providing lead-free and reliable interconnections will be useful for gas sensor fabricated on LTCC substrate. The FEM results are useful for optimizing the design for developing low-power LTCC hotplate.

Adherence and bonding mechanism between LTCC and thick film can be used to provide interconnections for LTCC devices. Methodology for providing such interconnections is discussed.

A new concept of 3D‐electronic packaging is presented: Si‐on‐Si multi‐chip module flip‐chip technology with arrays of fine etched and filled vertical electrical interconnections (vias). Arrays of vias with a high number of interconnections, and not only peripheral interconnections are used. A 3D Si‐on‐Si stack package demonstrator has been realized consisting of four Si‐substrates each representing a system level and containing four thinned and flip‐chip assembled chips. The chips are flip‐chip mounted on the flat side of the Si‐substrates. When interconnecting the Si‐substrates by bump technology the chips submerge into cavities on the rear side of the adjacent Si‐substrate. The chips also test the technology and quality of the electronic packaging, and therefore contain a set of thin film heaters, junctions for temperature measuring, Al‐meanders for stress and strain measuring and daisy chains for conduction path monitoring.

The purpose of this paper is to provide a historical perspective and framework for appreciating the evolution of 3D interconnection technologies from past to present.

A literature and patent search was performed to find the origins of 3D interconnections to find and credit work that was performed in the early electronics industry which presaged the development of the current generation 3D solutions.

The origins of 3D interconnections have roots that date to the beginnings of electronic interconnections if the earlier solutions are viewed in proper perspective. For example, early telegraphy and telephony interconnections strung from pole to pole across large expanses of terrain were clearly 3D interconnections on a very macro scale but those solutions scaled down are not that dissimilar to what is being done today in some advanced interconnection technologies.

The pioneers of the electronics industry broke a trail which has been widened, paved and branched by all who have followed them. Granted that the branches have led to new high‐worth discoveries but acknowledging the past and taking instruction from it is important, even necessary, to assure that future developments do not continually “reinvent the wheel”.

The paper traces, in brief fashion, the history of 3D interconnections providing examples of solutions which predate some of the current generation solutions which appear, in some cases, quite similar to those developed or proposed nearly half century ago. Knowing the past is vital to understanding and shaping the future.

The purpose of this paper is to fabricate a new Cu-Sn-Ni-Cu interconnection microstructure for electromigration studies in 3D integration.

The Cu-Sn-Ni-Cu interconnection microstructure is fabricated by a three-mask photolithography process with different electroplating processes. This microstructure consists of pads and conductive lines as the bottom layer, Cu-Sn-Ni-Cu pillars with the diameter of 10-40 μm as the middle layer and Cu conductive lines as the top layer. A lift-off process is adopted for the bottom layer. The Cu-Sn-Ni-Cu pillars are fabricated by photolithography with sequential electroplating processes. To fabricate the top layer, a sputtered Cu layer is introduced to prevent the middle-layer photoresist from being developed. With the final Cu electroplating processes, the Cu-Sn-Ni-Cu interconnection microstructure is successfully achieved.

The surface morphology of Cu-Sn pillars consists of densely packed clusters which are formed by an ordered arrangement of tetragonal Sn grains. The diffusion of Cu atoms into the Sn phases is observed at the Cu/Sn interface. Furthermore, the obtained Cu-Sn-Ni-Cu pillars have a flat surface with an average roughness of 13.9 nm. In addition, the introduction of Ni layer between the Sn and the top Cu layers in the Cu-Sn-Ni-Cu pillars can mitigate the diffusion of Cu atoms into Sn phases. The process is verified by checking the electrical performance using four-point probe measurements.

The method described in this paper which combined a three-mask photolithography process with sequential Cu, Sn, Ni and Cu electroplating processes provides a new way to fabricate the interconnection microstructure for future electromigration studies.

The purpose of this paper is to discuss the use of epoxy‐based conducting adhesives in z‐axis interconnections.

A variety of conductive adhesives with particle sizes ranging from 80 nm to 15 μm were laminated into printed wiring board substrates. SEM and optical microscopy were used to investigate the micro‐structures, conducting mechanism and path. The mechanical strength of the various adhesives was characterized by 90° peel test and measurement of tensile strength. Reliability of the adhesives was ascertained by IR‐reflow, thermal cycling, pressure cooker test (PCT), and solder shock. Change in tensile strength of adhesives was within 10 percent after 1,000 cycles of deep thermal cycling (DTC) between −55 and 125°C.

The volume resistivity of copper, silver and low‐melting point (LMP) alloy based paste were 5 × 10⁻⁴, 5 × 10⁻⁵ and 2 × 10⁻⁵ Ω cm, respectively. Volume resistivity decreased with increasing curing temperature. Adhesives exhibited peel strength with Gould's JTC‐treated Cu as high as 2.75 lbs/in. for silver, and as low as 1.00 lb/in. for LMP alloy. Similarly, tensile strength for silver, copper and LMP alloy were 3,370, 2,056 and 600 ψ, respectively. There was no delamination for silver, copper and LMP alloy samples after 3X IR‐reflow, PCT, and solder shock. Among all, silver‐based adhesives showed the lowest volume resistivity and highest mechanical strength. It was found that with increasing curing temperature, the volume resistivity of the silver‐filled paste decreased due to sintering of metal particles.

As a case study, an example of silver‐filled conductive adhesives as a z‐axis interconnect construction for a flip‐chip plastic ball grid array package with a 150 μm die pad pitch is given.

A high‐performance Z‐interconnect package can be provided which meets or exceeds JEDEC level requirements if specific materials, design, and manufacturing process requirements are met, resulting in an excellent package that can be used in single and multi‐chip applications. The processes and materials used to achieve smaller feature dimensions, satisfy stringent registration requirements, and achieve robust electrical interconnections are discussed.

3D chip stacking is a key technology for 3D integration in which two or more chips are stacked with vertical interconnections. In the case of multi chip stacking with fine pitch microbump connections, capillary dispensing presents big limitations in terms of cost and processability. The purpose of this paper is to describe the way in which wafer‐level underfill (WLUF) process development was carried out with particular emphasis on microbump height coplanarity, bonding pressure distribution and the alignment of the microbumps. A three factorial design of experiment (DOE) was also conducted to enhance the understanding of the factors impacting the WLUF process such as bonding pressure, temperature and time on reliability test.

B‐staged WLUF was laminated on an 8″ wafer with a 30 μm pitch bump structure of 8 μm Cu/5 μm Sn2.5Ag Pb‐free solder. After wafer dicing, the chip with the WLUF was assembled on a substrate chip with the same bump structure using a high accuracy bonder. The substrate chip had metalisation (wiring) to enable evaluation of the electrical characteristics of the bonded daisy chain chips as they varied with material bonding process conditions and reliability testing.

The WLUF bonding process development pertaining to the processability and reliability for the flip chip assembly using Cu/SnAg microbumps was successful in this work.

The development of a WLUF bonding process that offers reliability for flip chip assembly using Cu/SnAg microbumps has been presented in this work. The critical steps, such as alignment of the WLUF coated chip with the substrate chip and void elimination, which enable this technology to work were optimised.

This paper aims to realize the vertical interconnection in 3D radio frequency (RF) circuit by coaxial transitions with broad working bandwidth and small signal loss.

An advanced packaging method, 12-inch wafer-level through-mold-via (TMV) additive manufacturing, is used to fabricate a 3D resin-based coaxial transition with a continuous ground wall (named resin-coaxial transition). Designation and simulation are implemented to ensure the application universality and fabrication feasibility. The outer radius R of coaxial transition is optimized by designing and fabricating three samples.

The fabricated coaxial transition possesses an inner radius of 40 µm and a length of 200 µm. The optimized sample with an outer radius R of 155 µm exhibits S11 < –10 dB and S21 > –1.3 dB at 10–110 GHz and the smallest insertion loss (S21 = 0.83 dB at 77 GHz) among the samples. Moreover, the S21 of the samples increases at 58.4–90.1 GHz, indicating a broad and suitable working bandwidth.

The wafer-level TMV additive manufacturing method is applied to fabricate coaxial transitions for the first time. The fabricated resin-coaxial transitions show good performance up to the W-band. It may provide new strategies for novel designing and fabricating methods of RF transitions.

The purpose of this paper is to demonstrate a novel 3D system-in-package (SiP) approach. This new packaging approach is based on stacked silicon submount technology. As demonstrators, a smart lighting module and a sensor systems were successfully developed by using the fabrication and assembly process described in this paper.

The stacked module consists of multiple layers of silicon submounts which can be designed and fabricated in parallel. The 3D stacking design offers higher silicon efficiency and miniaturized package form factor. This platform consists of silicon submount design and fabrication, module packaging, system assembling and testing and analyzing.

In this paper, a smart light emitting diode system and sensor system will be described based on stacked silicon submount and 3D SiP technology. The integrated smart lighting module meets the optical requirements of general lighting applications. The developed SiP design is also implemented into the miniaturization of particular matter sensors and gas sensor detection system.

SiP has great potential of integrating multiple components into a single compact package, which has potential implementation in intelligent applications.

The purpose of this paper is to present a hybrid manufacturing system that integrates stereolithography (SL) and direct print (DP) technologies to fabricate three‐dimensional (3D) structures with embedded electronic circuits. A detailed process was developed that enables fabrication of monolithic 3D packages with electronics without removal from the hybrid SL/DP machine during the process. Successful devices are demonstrated consisting of simple 555 timer circuits designed and fabricated in 2D (single layer of routing) and 3D (multiple layers of routing and component placement).

A hybrid SL/DP system was designed and developed using a 3D Systems SL 250/50 machine and an nScrypt micro‐dispensing pump integrated within the SL machine through orthogonally‐aligned linear translation stages. A corresponding manufacturing process was also developed using this system to fabricate 2D and 3D monolithic structures with embedded electronic circuits. The process involved part design, process planning, integrated manufacturing (including multiple starts and stops of both SL and DP and multiple intermediate processes), and post‐processing. SL provided substrate/mechanical structure manufacturing while interconnections were achieved using DP of conductive inks. Simple functional demonstrations involving 2D and 3D circuit designs were accomplished.

The 3D micro‐dispensing DP system provided control over conductive trace deposition and combined with the manufacturing flexibility of the SL machine enabled the fabrication of monolithic 3D electronic structures. To fabricate a 3D electronic device within the hybrid SL/DP machine, a process was developed that required multiple starts and stops of the SL process, removal of uncured resin from the SL substrate, insertion of active and passive electronic components, and DP and laser curing of the conductive traces. Using this process, the hybrid SL/DP technology was capable of successfully fabricating, without removal from the machine during fabrication, functional 2D and 3D 555 timer circuits packaged within SL substrates.

Results indicated that fabrication of 3D embedded electronic systems is possible using the hybrid SL/DP machine. A complete manufacturing process was developed to fabricate complex, monolithic 3D structures with electronics in a single set‐up, advancing the capabilities of additive manufacturing (AM) technologies. Although the process does not require removal of the structure from the machine during fabrication, many of the current sub‐processes are manual. As a result, further research and development on automation and optimization of many of the sub‐processes are required to enhance the overall manufacturing process.

A new methodology is presented for manufacturing non‐traditional electronic systems in arbitrary form, while achieving miniaturization and enabling rugged structure. Advanced applications are demonstrated using a semi‐automated approach to SL/DP integration. Opportunities exist to fully automate the hybrid SL/DP machine and optimize the manufacturing process for enhancing the commercial appeal for fabricating complex systems.

This work broadly demonstrates what can be achieved by integrating multiple AM technologies together for fabricating unique devices and more specifically demonstrates a hybrid SL/DP machine that can produce 3D monolithic structures with embedded electronics and printed interconnects.