Search results

This paper presents a VHDL‐AMS based genetic optimisation methodology for fuzzy logic controllers (FLCs) used in complex automotive systems and modelled in mixed physical domains. A case study applying this novel method to an active suspension system has been investigated to obtain a new type of fuzzy logic membership function with irregular shapes optimised for best performance.

The geometrical shapes of the fuzzy logic membership functions are irregular and optimised using a genetic algorithm (GA). In this optimisation technique, VHDL‐AMS is used not only for the modelling and simulation of the FLC and its underlying active suspension system but also for the implementation of a parallel GA directly in the system testbench.

Simulation results show that the proposed FLC has superior performance in all test cases to that of existing FLCs that use regular‐shape, triangular or trapezoidal membership functions.

The test of the FLC has only been done in the simulation stage, no physical prototype has been made.

This paper proposes a novel way of improving the FLC's performance and a new application area for VHDL‐AMS.

The purpose of this paper is to integrate the function of a speed controller for induction motor (IM) drive, such as the speed PI controller, the current vector controller, the slip speed estimator, the space vector pulse width modulation scheme, the quadrature encoder pulse, and analog to digital converter interface circuit, etc. into one field programmable gate array (FPGA).

First, the mathematical modeling of an IM drive, the field-oriented control algorithm, and PI controller are derived. Second, the very high speed IC hardware description language (VHDL) is adopted to describe the behavior of the algorithms above. Third, based on electronic design automation simulator link, a co-simulation work constructed by ModelSim and Simulink is applied to verify the proposed VHDL code for the speed controller intellectual properties (IP). Finally, the developed VHDL code will be downloaded to the FPGA for further control the IM drive.

In realization aspect, it only needs 5,590 LEs, 196,608 RAM bits, and 14 embedded 9-bit multipliers in FPGA to build up a speed control IP. In computational power aspect, the operation time to complete the computation of the PI controller, the slip speed estimator, the current vector controller are only 0.28 μs, 0.72 μs, and 0.96 μs, respectively.

Fast computation in FPGA can speed up the speed response of IM drive system to increase the running performance.

This is the first time to realize all the function of a speed controller for IM drive within one FPGA.

The present work aims to explain how the nonlinear average model can be used in power electronic integration design as a behavioral model.

The nonlinear average model is used in power electronic integration design as a behavioral model, where it is applied to a voltage source inverter based on IGBTs. This model was chosen because it takes into account the nonlinearity of the power semiconductor components and the wiring circuit effects, which can be formalized by the virtual delay concept. In addition, the nonlinear average model cannot distinguish between slow and quick variables and this is an important feature of the model convergence.

The paper studies extensively the construction of the nonlinear average model algorithm theoretically. Detailed explanations of the application of this model to voltage source inverter design are provided. The study demonstrates how this model illustrates the effect of the nonlinearity of the power semiconductor components' characteristics on dynamic electrical quantities. It also predicts the effects due to wiring in the inverter circuit.

More simulations and experimental analysis are still necessary to improve the model's accuracy, by using other static characteristic approaches, and to validate the applicability of the model to different converter topologies.

The paper formulates a simple nonlinear average model algorithm, discussing each step. This model was described by VHDL‐AMS. On the one hand, it will assist theoretical and practical research on different topologies of power electronic converters, particularly in power integration systems design such as the integrated power electronics modules (IPEM). On the other hand, it will give designers a more precise behavioral model with a simpler design process.

The nonlinear average model used in power electronic integration design as behavioral model is a novel approach. This model reduces computational costs significantly, takes physical effects into account and is easy to implement.

The inverse kinematics in robot manipulator have to handle the arctangent and arccosine function. However, the two functions are complicated and need much computation time so that it is difficult to be realized in the typical processing system. The purpose of this paper is to solve this problem by using Field Programmable Gate Array (FPGA) to speed up the computation power.

The Taylor series expansion method is firstly applied to transfer arctangent and arccosine function to a polynomial form. And Look-Up Table (LUT) is used to store the parameters of the polynomial form. Then the behavior of the computation algorithm is described by Very high-speed IC Hardware Description Language (VHDL) and a co-simulation using ModelSim and Simulink is applied to evaluate the correctness of the VHDL code.

The computation time of arctangent and arccosine function using by FPGA need only 320 and 420 ns, respectively, and the accuracy is <0.01°.

Fast computation in arctangent and arccosine function can speed up the motion response of the real robot system when it needs to perform the inverse kinematics function.

This is the first time such to combine the Taylor series method and LUT method in the computation the arctangent and arccosine function as well as to implement it with FPGA.

With the rapid development in wired and wireless networks, the demand for network security system is rising rapidly due to more and more new applications introduced. The main factors that rate the encryption algorithms are its ability to secure and protect data against attacks, its speed and efficiency. In this paper, a reconfigurable network security design using multi-mode data encryption standard (DES) algorithm has been implemented with low complexity and low cost, which will also reduce the speed. The paper aims to discuss these issues.

The design can be easily reconfigured to 3DES (triple DES) which is more secure and more powerful in encryption and decryption, as one of the trick in designing 3DES is to reuse three instances of DES. The design can be used for wired and wireless network applications, and it has been described using VHDL and implemented in a reconfigurable Programmable System-on-Chip (PSoC). The hardware implementation has targeted Xilinx Spartan XC3S700-AN FPGA device.

The main idea of reducing the complexity for the hardware implementation is by optimizing the number of logic gates and LUTs of the design. The number of logic gates can be decreased by changing the way of writing the VHDL code and by optimizing the size of the chip.

The design has been tested in simulation and hardware levels, and the simulation results and performance are discussed.

Matrix product is a compute bound problem that can be efficiently handled by elementary systolic algorithms. From a theoretical point of view, most of the algorithms are very simple and sometimes even trivial. However, the task of designing efficient implementation on a fixed‐connection network, such as on FPGA where resources are very limited, has been more demanding, and sometimes quite tedious. The objective of this paper is twofold: we first describe a full‐systolic algorithm for matrix product that has the merit over its existing counterparts, to require no preloading of input data into elementary processors (EPs) and generates output data only from boundary EPs. The resulting architecture can accept an uninterrupted stream of input data and produces an uninterrupted one with a latency of 2N‐1 for N×N matrix product. This architecture is also scalable and complies with the constraint of problem‐size independence (ψ). Secondly, we present a methodology for generating a family of very compact MP arrays on FPGA based essentially upon manual mapping at CLB level coupled with VHDL structural level.

To present a new approach for improvement and optimization of synchronous claw‐pole alternators without changing the general machine design.

Various changes on the magnetically relevant parts of the machine design have been discussed formerly to achieve improved electromagnetic and acoustic behavior. The electrical part of the machine is considered in this paper, varying the stator winding arrangement to achieve optimized behavior.

Provides information about motivation and the methodology of the optimization process. Presents the entire analysis, covering idea, technical and computational implementation as well as verification.

It describes a method based on the utilization of specific, partly self‐generated software, which perhaps limits its usefulness if mentioned tools are unavailable. However, the presented basic method is to be used generally.

This paper presents a promising approach to further optimize the design of synchronous claw‐pole alternators without major changes in the machine design.

This paper presents a prediction on the impact of technology scaling on phase‐locked loop (PLL) performance behaviour. Power and maximum operating frequency of an Analogue PLL and a Type II phase‐frequency detector (PFD)‐based PLL from which the behaviours of other PLLs derived from the two architectures can be estimated, are analysed and their future behaviours as a function of technology are predicted.

Analogue models were developed and Mentor Graphics VHDL‐AMS mixed‐signal simulations were performed on the two PLL architectures. Behavioural power and frequency equations as a function of technology were derived based on thorough data and graphical analyses.

A prediction of PLL frequency and power dissipation as a function of technology for two main PLL architectures.

The parameters in each equation derived should include other contributing factors as well as other design approaches such as multi‐VDD, multi‐Vth, etc. future work should also include prediction of jitter and phase noise for the two main PLL topologies.

This paper is of high significance in PLL design. The predicted equations could be used to reduce a major portion of a PLL designers' design time when choosing a PLL topology, and help them predict the impact of technology on the performance of the chosen architecture.

The purpose of this paper is to show the evolution of microsystems together with modeling methods in the space of dozen years as a result of finished research in the frame of several projects.

In this paper several approaches are presented. First, microsystems were built in multi project wafer technology. They were demonstrators like micromotor, micromirrors or micropumps modeled using dedicated design tool. A multi purpose chip was also designed using HDL description and FEM simulations. The next project concerned chemical sensors, where specialized models were developed and implemented in VHDL‐AMS in order to perform multidomain behavioral simulations. Dedicated tools were also developed for medical applications.

The evolution of MEMS technology is strictly connected with simulation and modeling methods. The success and short time to market need fast and accurate simulation methods. This paper shows that the approach depends on application. Moreover, it is connected with the access to the technology.

This paper presents a brief overview on projects performed in DMCS‐TUL department. It shows the evolution of modeling methods and technology used in developing and fabrication of microsystems for various applications.

The purpose of this paper is to inspect strategic placing of different signal processing techniques like wavelet transform (WT), discrete Hilbert transform (DHT) and fast Fourier transform (FFT) to acquire the qualitative detection of rotor fault in a variable frequency drive-fed induction motor under challenging low slip conditions.

The algorithm is developed using Q2.14 bit format of Xilinx System Generator (XSG)-DSP design tool in MATLAB. The developed algorithm in XSG-MATLAB can be implemented easily in field programmable gate array, as a provision to generate the necessary VHDL code is available by its graphical user interface.

The applicability of WT is ensured by the effective procedure of base wavelet selection, which is the novelty of the work. It is found that low-order Daubechies (db) wavelets show decent shape matching with current envelope rather than raw current signal. This fact allows to use db1-based discrete wavelet transform-inverse discrete wavelet transform, where economic and multiplier-less design is possible. Prominent identity of 2sf_s component is found even at low FFT points due to the application of suitable base wavelet.

The proposed method is found to be effective and hardware-friendly, which can be used to design a low-cost diagnostic instrument for industrial applications.