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Article
Publication date: 1 August 1996

V. Kripesh, S.K. Bhatnagar, H. Osterwinter and W. Gust

Temperature humidity acceleration factors for surface conductance areobtained to relate the reliability of film conductors formed by different processes. Analytical expressionsfor…

197

Abstract

Temperature humidity acceleration factors for surface conductance are obtained to relate the reliability of film conductors formed by different processes. Analytical expressions for acceleration factor are evolved for both screen‐printed and laser micromachined conductor samples. The rapid solidification of metal conductors due to laser micromachining and its effect on surface conductance are also studied. An analytical expression for the most common accelerated test condition (85°C, 85% relative humidity) is also derived for both screen‐printed and laser micromachined samples.

Details

Microelectronics International, vol. 13 no. 2
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 1 December 1996

V. Kripesh, S.K. Bhatnagar, H. Osterwinter and W. Gust

A laser ablation technique has been used to fabricate conductor patterns on a 96%alumina substrate to evolve passive fine‐line components and structures. This paper reports the…

145

Abstract

A laser ablation technique has been used to fabricate conductor patterns on a 96% alumina substrate to evolve passive fine‐line components and structures. This paper reports the method of fabricating better fine‐line passive components for hybrid microelectronics application. The effect of a laser beam on the conductor and 96% alumina (Al2O3) substrate was studied in detail. Three predominant structures — namely debris, ablation border and irradiated bottom layer — were seen on the patterns. A detailed study of the dendritic growth caused by electrochemical migration on conductor lines fabricated by conventional screen printing and by laser ablation techniques is also reported.

Details

Microelectronics International, vol. 13 no. 3
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 8 February 2011

S.L. Tay, A.S.M.A. Haseeb and Mohd Rafie Johan

The purpose of this paper is to investigate the effects of addition Co nanoparticles on the characteristic properties of Sn‐3.8Ag‐0.7Cu solder.

Abstract

Purpose

The purpose of this paper is to investigate the effects of addition Co nanoparticles on the characteristic properties of Sn‐3.8Ag‐0.7Cu solder.

Design/methodology/approach

Cobalt (Co) nanoparticles were added to Sn‐Ag‐Cu solders by thoroughly blending various weight percentages (0‐2.0 wt%) of Co nanoparticles with near eutectic SAC387 solder paste. Blending was done mechanically for 30 min to ensure a homogeneous mixture. The paste mixture was then reflowed on a hot plate at 250°C for 45 s. The melting points of nanocomposite solder were determined by differential scanning calorimetry. Spreading rate of nanocomposite was calculated following the JIS Z3198‐3 standard. The wetting angle was measured after cross‐sectional metallographic preparation.

Findings

No significant change in melting point of the solder was observed as a result of Co nanoparticle addition. The wetting angles of the solder increased with the addition of nanoparticles, while the spreading rate decreased. Although the wetting angle increased, the values were still within the acceptable range. Scanning micrograph observations revealed that the as‐solidified microstructure of the composite solder was altered by the addition of Co nanoparticles. Microhardness of the solders slightly increased upon Co nanoparticles addition to SAC387.

Originality/value

The paper demonstrates that a simple process like paste mixing can be used to incorporate nanoparticles into solder.

Details

Soldering & Surface Mount Technology, vol. 23 no. 1
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 16 August 2013

Yuanming Chen, Wei He, Guoyun Zhou, Zhihua Tao, Yang Wang and Daojun Luo

Pb‐free soldering challenged printed circuit board (PCB) assembly with high temperature. The purpose of this paper is to explain the failure mechanism of printed circuit board…

Abstract

Purpose

Pb‐free soldering challenged printed circuit board (PCB) assembly with high temperature. The purpose of this paper is to explain the failure mechanism of printed circuit board (PCB) assembly with solder bubbles of vias to avoid the problems of via‐drilling defects and solder joint failure.

Design/methodology/approach

The failure of PCB vias with solder bubbles was investigated through cross sections and SEM microstructure inspection, TMA measurement, moisture absorption analysis and DSC measurement. The moisture absorption and CTE of FR4 laminate matched with manufacturing requirement to avoid the effects of solder bubbles. The effects of via drilling with a dull drill bit were compared to that with a new drill bit.

Findings

The moisture absorbed inside holes of via plating layers could be exposed to induce solder bubbles during Pb‐free soldering assembly and dull drill bits should be prevented during the drilling process to avoid the no‐bearing drilling effects.

Originality/value

The failure of PCB vias is not only involved in the voiding in solder joints but manufacturing processes of PCB. The paper designs an approach to analyse the properties of PCB materials and the drilling effects of vias to find out the mechanism resulting in solder bubbles of vias. The problem of drill bits should be considered to prevent the moisture absorbed in drilling vias with defects.

Details

Circuit World, vol. 39 no. 3
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 28 July 2021

Mardiana Said, Muhammad Firdaus Mohd Nazeri, Nurulakmal Mohd Sharif and Ahmad Azmin Mohamad

This paper aims to investigate the morphology and tensile properties of SAC305 solder alloy under the influence of microwave hybrid heating (MHH) for soldering at different…

Abstract

Purpose

This paper aims to investigate the morphology and tensile properties of SAC305 solder alloy under the influence of microwave hybrid heating (MHH) for soldering at different microwave parameters.

Design/methodology/approach

Si wafer was used as susceptor in MHH for solder reflow. Microwave operating power for medium and high ranging from 40 to 140 s reflow time was used to investigate their effect on the microstructure and strength of SAC305/Cu solder joints. The morphology and elemental composition of the intermetallic compound (IMC) joint were evaluated on the top surface and cross-sectional view.

Findings

IMC formation transformed from scallop-like to elongated scallop-like structure for medium operating power and scallop-like to planar-like structure for high operating power when exposed to longer reflow time. Compositional and phase analysis confirmed that the observed IMCs consist of Cu6Sn5, Cu3Sn and Ag3Sn. A thinner IMC layer was formed at medium operating power, 80 s (2.4 µm), and high operating power, 40 s (2.5 µm). The ultimate tensile strength at high operating power, 40 s (45.5 MPa), was 44.9% greater than that at medium operating power, 80 s (31.4 MPa).

Originality/value

Microwave parameters with the influence of Si wafer in MHH in soldering have been developed and optimized. A microwave temperature profile was established to select the appropriate parameter for solder reflow. For this MHH soldering method, the higher operating power and shorter reflow time are preferable.

Details

Soldering & Surface Mount Technology, vol. 34 no. 1
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 10 May 2011

John H. Lau

The purpose of this paper is to focus on through‐silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on…

4226

Abstract

Purpose

The purpose of this paper is to focus on through‐silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented.

Design/methodology/approach

This design addresses the electronic packaging of 3D IC integration with a passive TSV interposer for high‐power, high‐performance, high pin‐count, ultra fine‐pitch, small real‐estate, and low‐cost applications. To achieve this, the design uses chip‐to‐chip interconnections through a passive TSV interposer in a 3D IC integration system‐in‐package (SiP) format with excellent thermal management.

Findings

A generic, low‐cost and thermal‐enhanced 3D IC integration SiP with a passive interposer has been proposed for high‐performance applications. Also, the origin of 3D integration and the overview and outlook of 3D Si integration and 3D IC integration have been presented and discussed. Some important results and recommendations are summarized: the TSV/redistribution layer (RDL)/integrated passive devices passive interposer, which supports the high‐power chips on top and low‐power chips at its bottom, is the gut and workhorse of the current 3D IC integration design; with the passive interposer, it is not necessary to “dig” holes on the active chips. In fact, try to avoid making TSVs in the active chips; the passive interposer provides flexible coupling for whatever chips are available and/or necessary, and enhances the functionality and possibly the routings (shorter); with the passive interposer, the TSV manufacturing cost is lower because the requirement of TSV manufacturing yield is too high (>99.99 percent) for the active chips to bear additional costs due to TSV manufacturing yield loss; with the passive interposer, wafer thinning and thin‐wafer handling costs (for the interposer) are lower because these are not needed for the active chips and thus adds no cost due to yield loss; with the current designs, all the chips are bare; the packaging cost for individual chips is eliminated; more than 90 percent of heat from the 3D IC integration SiP is dissipated from the backside of high‐power chips using a thermal interface material and heat spreader/sink; the appearance and footprint of current 3D IC integration SiP designs are very attractive to integrated device manufactures, original equipment manufactures, and electronics manufacturing services (EMS) because they are standard packages; and underfills between the copper‐filled TSV interposer and the high‐ and low‐power chips are recommended to reduce creep damage of the lead‐free microbump solder joints and prolong their lives.

Originality/value

The paper's findings will be very useful to the electronic industry.

Details

Microelectronics International, vol. 28 no. 2
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 11 May 2010

John Lau, Ricky Lee, Matthew Yuen and Philip Chan

The purpose of this paper is to propose new 3D light emitting diodes (LED) and integrated circuits (IC) integration packages.

1322

Abstract

Purpose

The purpose of this paper is to propose new 3D light emitting diodes (LED) and integrated circuits (IC) integration packages.

Design/methodology/approach

These packages consist of the multi‐LEDs and active IC chip such as the application specific IC, LED driver, processor, memory, radio frequency, sensor, or power controller in a 3D manner. The assembly processes of these packages are also presented and discussed.

Findings

The advantages of these 3D integration packages are found to be: better performance, lower cost, less footprint, lighter package, and smaller form factor.

Originality/value

A thermal management system for 3D IC and LEDs integration packages is proposed.

Details

Microelectronics International, vol. 27 no. 2
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 5 May 2015

Mingzhi Dong, Fabio Santagata, Robert Sokolovskij, Jia Wei, Cadmus Yuan and Guoqi Zhang

This study aims to provide a flexible and cost-effective solution of 3D heterogeneous integration for applications such as micro-electro-mechanical system (MEMS) applications and…

Abstract

Purpose

This study aims to provide a flexible and cost-effective solution of 3D heterogeneous integration for applications such as micro-electro-mechanical system (MEMS) applications and smart sensor systems.

Design/methodology/approach

A novel 3D system-in-package (SiP) based on stacked silicon submount technology was successfully developed and well-demonstrated by the fabrication and assembly process of a selected smart lighting module.

Findings

The stacked module consists of multiple layers of silicon submounts which can be designed and fabricated in parallel. The bonding and interconnecting process is quite simple and does not require complicated equipment. The 3D stacking design offers higher silicon efficiency and miniaturized package form factor. The submount wafer can be assembled and tested at the wafer level, thus reducing the cost and improving the yield.

Research limitations/implications

The embedding design presented in this paper is applicable for modules with limited number of passives. When it comes to cases with more passive devices, new process needs to be developed to achieve fast, inexpensive and reliable assembly.

Originality/value

The presented 3D SiP design is novel for applications such as smart lighting, Internet of Things, MEMS systems, etc.

Details

Microelectronics International, vol. 32 no. 2
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 1 June 2005

Günter Grossmann, Joy Tharian, Pascal Jud and Urs Sennhauser

The goal of this work is to evaluate the feasibility of soldering tin‐silver‐copper balled BGAs using tin‐lead‐based solder and to investigate the influence of different…

1678

Abstract

Purpose

The goal of this work is to evaluate the feasibility of soldering tin‐silver‐copper balled BGAs using tin‐lead‐based solder and to investigate the influence of different production parameters on the microstructure of the solder joint.

Design/methodology/approach

The soldering of the BGAs was done with various temperature profiles and two conveyor speeds under a nitrogen atmosphere in a full convection oven. One specimen from each temperature/time combination was cross‐sectioned. The cross sections were analysed with optical microscopy, scanning electron microscopy with energy dispersive X‐ray spectroscopy (SEM/EDS) at 30 kV and focused ion beam microscopy (FIB).

Findings

The cross sections show a metallurgical bond between the solder and the tin‐silver‐copper balls of the BGA, even at a peak reflow temperature of 210°C. However, the balls alloy only partially with the solder, as the liquidus of tin‐silver‐copper balls is 217°C. As soon as the peak temperature exceeds the liquidus of the ball, the solder is totally dissolved in the material of the ball. A reflow profile with a peak temperature of about 230°C on the BGA gives a homogenous reaction of the solder with the ball with a minimum formation of voids.

Research limitations/implications

The dependence of varying reflow parameters on reliability requires detailed study. Especially the effect of a partially melted ball on the degradation of the solder joint needs to be investigated.

Originality/value

From the findings, it can be said that soldering lead‐free balls with tin‐lead solder is possible. This is useful during the transitional period that the industry is in at the moment. More and more component manufacturers are changing their components to lead‐free, often without notice to the customer. If a production line is still running a tin‐lead process it is essential to know how to process these components with tin‐lead solder.

Details

Soldering & Surface Mount Technology, vol. 17 no. 2
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 1 April 2003

S.T. Nurmi, J.J. Sundelin, E.O. Ristolainen and T. Lepistö

Lead‐free soldering is becoming a common practice in the electronics industry because of the growing general opposition to lead‐containing solders. The reliability of lead‐free…

Abstract

Lead‐free soldering is becoming a common practice in the electronics industry because of the growing general opposition to lead‐containing solders. The reliability of lead‐free solders has been studied a lot recently, but knowledge of it is still incomplete and many issues related to them are under heavy debate. This paper presents results from a study of the formation of voids with regard to the number of reflow cycles in three different kinds of solder joints: first the ones prepared with lead‐free solder paste and lead‐free plastic ball grid array (PBGA) components, next the ones prepared with lead‐free solder paste and tin‐lead‐silver PBGA components, and last the ones prepared with tin‐lead solder paste and tin‐lead‐silver PBGA components.

Details

Soldering & Surface Mount Technology, vol. 15 no. 1
Type: Research Article
ISSN: 0954-0911

Keywords

1 – 10 of 30