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Studies of solder‐bumped flip chips on organic substrates reported in the literature have so far suggested the necessity of a polymeric underfill to compensate for the large thermal mismatch between the silicon and the substrate. In this company's target applications of this process, the underfill not only has to meet the much published mechanical and chemical requirements, but also has to flow through a vertical clearance of 0.020 to 0.0375 mm quickly as well as being cured in a relatively short time. The evaluation of the underfill materials starts with some basic understanding of how the different ingredients in the underfill formulation might affect its physical and chemical properties. The flow characteristics of the underfills were a first priority in the selection. A detailed thermal‐mechanical analysis then helped to determine the optimal cure schedule with the desired physical properties. A simple test die/test board system has been designed to evaluate how the underfill might work in a quasi‐production process and to allow for subsequent reliability evaluation. This paper highlights the ‘pluses and minuses’ of the currently available commercial underfills in relation to the optimisation of a high‐volume production process.

The impact of underfill properties on the thermomechanical reliability of flip chip on board (FCOB) assembly is addressed in this paper. FCOB assemblies using three underfill encapsulants were subjected to a thermal cycling test. The performance of the underfill encapsulants was assessed by a statistical analysis of the failure distribution of the FCOB assemblies. The failure modes in the thermal cycling test were found to be solder joint cracks, delamination at underfill/chip passivation interface, and underfill internal cracks. An attempt was made to correlate these failures with underfill properties such as the coefficient of thermal expansion (CTE), modulus, glass transition temperature (Tg), and adhesive strength to the chip. Additionally, nonlinear finite element analysis (FEA) was conducted to verify the experimental results.

No‐Flow or fluxing underfills will play a key role in the future of flip chip processing. Properly formulated No‐Flow Underfills decrease manufacturing time and cost of producing flip chip packages. The reliability and processing ability allows these underfills to be incorporated into many unique applications. Processing yields and reliability on ceramic, flex and organic substrates will allow No‐Flow Underfills to be used successfully in future Bluetooth and wireless telecommunication products. This work gives the reliability of a commercially available No‐Flow Underfill on three flip chip and two BGA/CSP test vehicles. A detailed failure mode analysis of the underfill was also performed.

This paper aims to study the relationship between the ball grid array (BGA) flip-chip underfilling process parameter and its void formation region.

A set of top-down scanning acoustic microscope images of BGA underfill is collected and void labelled. The labelled images are trained with a convolutional neural network model, and the performance is evaluated. The model is tested with new images, and the void area with its region is analysed with its dispensing parameter.

All findings were well-validated with reference to the past experimental results regarding dispensing parameters and their quantitative regional formation. As the BGA is non-uniform, 85% of the test samples have void(s) formed in the emptier region. Furthermore, the highest rating factor, valve dispensing pressure with a Gini index of 0.219 and U-type dispensing pattern set of parameters generally form a lower void percentage within the underfilling, although its consistency is difficult to maintain.

This study enabled manufacturers to forecast the void regional formation from its filling parameters and array pattern. The filling pressure, dispensing pattern and BGA relations could provide qualitative insights to understand the void formation region in a flip-chip, enabling the prompt to formulate countermeasures to optimise voiding in a specific area in the underfill.

The void regional formation in a flip-chip underfilling process can be explained quantitatively with indicative parameters such as valve pressure, dispensing pattern and BGA arrangement.

The purpose of this study is to investigate the effect of the adhesive force and density ratio using lattice Boltzmann method (LBM) during underfill process.

To deal with complex flow in underfill process, a framework is proposed to improve the lattice Boltzmann equation. The fluid flows with different density ratio and bump arrangement in underfill are simulated by the incorporated Carnahan–Starling (CS) equation of state (EOS). The numerical study conducted by finite volume method (FVM) and experimental results are also presented in each case at the different filling percentage for verification and validation purpose.

The numerical result is compared well with those acquired experimentally. Small discrepancy is detected in their flow profile. It was found that the adhesive force between fluid and solid was affected by the density ratio of the fluids and solder bump configuration. LBM has shown better adhesive force effect phenomenon on underfill process compared to FVM. LBM also demonstrated as a better tool to study the fluid flow in the underfill process.

This study provides a basis and insights into the impact of adhesive force and density ratio to the underfill process that will be advancing the future design of flip chip package. This study also provides superior guidelines, and the knowledge of how adhesive force is affected by flip chip package structure.

This study proposes the method to predict the adhesive force and density ratio effect for underfill flow in flip chip package. In addition, the proposed method has a good performance in representing the adhesive force during the underfill simulation for its natural physical basic. This study develops understanding of flow problems to attain high reliability for electronic assemblies.

This paper aims to present new analytical model for the filling times prediction in flip-chip underfill encapsulation process that is based on the surface energetic for post-bump flow.

The current model was formulated based on the modified regional segregation approach that consists of bump and post-bump regions. Both the expansion flow and the subsequent bumpless flow as integrated in the post-bump region were modelled considering the surface energy–work balance.

Upon validated with the past underfill experiment, the current model has the lowest root mean square deviation of 4.94 s and maximum individual deviation of 26.07%, upon compared to the six other past analytical models. Additionally, the current analytically predicted flow isolines at post-bump region are in line with the experimental observation. Furthermore, the current analytical filling times in post-bump region are in better consensus with the experimental times as compared to the previous model. Therefore, this model is regarded as an improvised version of the past filling time models.

The proposed analytical model enables the filling time determination for flip-chip underfill process at higher accuracy, while providing more precise and realistic post-bump flow visualization. This model could benefit the future underfill process enhancement and package design optimization works, to resolve the productivity issue of prolonged filling process.

The analytical underfill studies are scarce, with only seven independent analytical filling time models being developed to date. In particular, the expansion flow of detachment jump was being considered in only two previous works. Nonetheless, to the best of the authors’ knowledge, there is no analytical model that considered the surface energies during the underfill flow or based on its energy–work balance. Instead, the previous modelling on post-bump flow was based on either kinematic or geometrical that is coupled with major assumptions.

In land grid array hybrid or system in package type products passive integration on silicon dies are flip chip mounted on a laminate substrate using Pb‐free solder. To increase the solder bump fatigue life, underfill is applied. The application of underfill resulted in the occurrence of an unexpected and unwanted phenomenon: solder flowing out of the underfill during a second level reflow test. The occurrence of solder flow‐out seemed associated with moisturizing as part of a moisture sensitivity level assessment. The solder flow‐out is preceded by delamination, initiated by mismatch in coefficient of thermal expansion between copper through‐holes and laminate. This paper aims to describe the phenomenon and possible solutions by combining experiments with finite element (FE) simulations.

Ways to prevent this kind of overstress failures are investigated by design of experiments and observed trends are compared with thermo‐mechanical FE simulations. A significant contribution is made by through‐holes close to the bump and underfill fillet.

The FE simulations confirmed increased thermo‐mechanical induced stress levels by bad positioning of vias, underfill and solder. The integrity of the flip chip construction is substantially improved by optimising product design, underfill material and the associated assembly process.

This paper is a useful source of information on the causes of delamination and solder flow‐out.

The purpose of the study is to investigate the spatial aspects of underfill flow during the flip-chip encapsulation process, for instance, meniscus evolution and contact line jump (CLJ). Furthermore, a spatial-based void formation mechanism during the underfill flow was formulated.

The meniscus evolution of underfill fluid subtended between the bump array and the CLJ phenomenon were visualized numerically using the micro-mesh unit cell approach. Additionally, the meniscus evolution and CLJ phenomenon were modelled analytically based on the formulation of capillary physics. Meanwhile, the mechanism of void formation was explained numerically and analytically.

Both the proposed analytical and current numerical findings achieved great consensus and were well-validated experimentally. The variation effects of bump pitch on the spatial aspects were analyzed and found that the meniscus arc radius and filling distance increase with the pitch, while the subtended angle of meniscus arc is invariant with the pitch size. For larger pitch, the jump occurs further away from the bump entrance and takes longer time to attain the equilibrium meniscus. This inferred that the concavity of meniscus arc was influenced by the bump pitch. On the voiding mechanism, air void was formed from the air entrapment because of the fluid-bump interaction. Smaller voids tend to merge into a bigger void through necking and, subsequently, propagate along the underfill flow.

The microscopic spatial analysis of underfill flow would explain fundamentally how the bump design will affect the macroscopic filling time. This not only provides alternative visualization tool to analyze flow pattern in the industry but also enables the development of accurate analytical filling time model. Moreover, the void formation mechanism gave substantial insights to understand the root causes of void defects and allow possible solutions to be formulated to tackle this issue. Additionally, the microfluidics sector could also benefit from these spatial analysis insights.

Spatial analysis on underfill flow is scarcely conducted, as the past research studies mainly emphasized on the temporal aspects. Additionally, this work presented a new mechanism on the void formation based on the fluid-bump interaction, in which the formation and propagation of micro-voids were numerically visualized for the first time. The findings from current work provided fundamental information on the flow interaction between underfill fluid and solder bump to the package designers for optimization work and process enhancement.

The solder joint reliability of FC components on organic substrates is questionable unless underfill is used to relieve the thermal strains. Besides the mechanical protection, underfill provides the solder and I.C. surface with protection against the environment. Underfilling is however, time‐consuming and expensive. In an electrical sense, the underfill has no beneficial function and should, therefore, be considered as a ballast in an electronic assembly. However, to obtain a satisfactory level of reliability without underfill some novel methods are required. Wafer thinning is often performed to fit a die into a thin package, e.g. in smart cards. In this paper, the issue of thinning a package is studied utilizing 3D finite element method models. Various die and board thicknesses are evaluated with respect to their effect on the reliability of FC solder bumps. In addition, a novel idea to increase the joint reliability is studied.

This paper aims to introduce a new indicative parameter of filling efficiency to quantify the performance and productivity of the flip-chip underfill encapsulation process. Additionally, the variation effect of the bump pitch of flip-chip on the filling efficiency was demonstrated to provide insight for flip-chip design optimization.

The filling efficiency was formulated analytically based on the conceptual spatial and temporal perspectives. Subsequently, the effect of bump pitch on filling efficiency was studied based on the past actual-scaled and current scaled-up underfill experiments. The latter scaled-up experiment was validated with both the finite volume method-based numerical simulation and analytical filling time model. Moreover, the scaling validity of scaled-up experiment was justified based on the similarity analysis of dimensionless number.

Through the scaling analysis, the current scaled-up experimental system is justified to be valid since the adopted scaling factor 40 is less than the theoretical scaling limit of 270. Furthermore, the current experiment was qualitatively well validated with the numerical simulation and analytical filling time model. It is found that the filling efficiency increases with the bump pitch, such that doubling the bump pitch would triple the efficiency.

The new performance indicative index of filling efficiency enables the package designers to justify the variation effect of underfill parameter on the overall underfill process. Moreover, the upper limit of scaling factor for scaled-up package was derived to serve as the guideline for future scaled-up underfill experiments.

The performance of underfill process as highlighted in this paper was never being quantified before in the past literatures. Similarly, the scaling limit that is associated to the scaled-up underfill experiment was never being reported elsewhere too.