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A new under bump metallurgy (UBM) solution consisting of the TiW‐, Au‐ and Ni‐layers for solder flip chip applications has been developed. The metallurgy, being based on the well‐known TAB metallisation procedure, was modified by producing the galvanic nickel layer on the top of the Au‐TiW metallisation. Nickel is needed between high Sn liquid solder bumps and the Au layer to prevent fast and extensive dissolution of thin Cu or Au layers and consequently excessive intermetallic formation. The flip chip joints were manufactured, employing both the 60Sn40Pb‐ and pure Sn‐bumped chips together with the new UBM, which is relatively easy to implement into volume production. The different ageing tests demonstrated that reliable joints can be produced by using the UBM. On the basis of the results obtained the new UBM was found to be a significant improvement in the production of reliable flip chip joints.

In flip‐chip interconnection on organic substrates using eutectic tin/lead solder bumps, a highly reliable under bump metallurgy (UBM) is required to maintain adhesion and solder wettability. Various UBM systems such as 1μm Al/0.2μm Ti/5μm Cu, 1μm Al/02μm Ti/1μm Cu, 1μm Al/0.2μm Ni/1μm Cu and 1μm Al/0.2μm Pd/1μm Cu, applied under eutectic tin/lead solder bumps, have been investigated with regard to their interfacial reactions and adhesion properties. The effects of the number of solder reflow cycles and the aging time on the growth of intermetallic compounds (IMCs) and on the solder ball shear strength were investigated. Good ball shear strength was obtained with 1μm Al/0.2μm Ti5μm Cu and 1μm Al/0.2μm Ni/1μm Cu even after four solder reflows or seven‐day aging at 150∞C. In contrast, 1μm Al/0.2μm Ti/1μm Cu and 1μm Al/0.2μm Pd/1μm Cu showed poor ball shear strength. The decrease of the shear strength was mainly due to the direct contact between solder and non‐wettable metals such as Ti and AL, resulting in a delamination. In this case, thin 1μm Cu and 0.2μm Pd diffusion barrier layers were completely consumed by Cu‐Sn and Pd‐Sn reaction.

Sn‐Pb and Sn‐Ag bumps (130 μm diameter, 250 μm pitch) made using an electroplating process were studied. As a preliminary experiment, the effects of current density and plating time on the Sn‐Pb and Sn‐Ag deposits were investigated. The morphology and composition of the plated surface were examined using scanning electron microscopy. The shape and thickness of the solder bumps were also compared. Bump shear testing was performed to measure the adhesion strength between the solder bumps and the under bump metallurgy. In electroplating, the Sn‐Ag plating thickness was proportional to the current density, while plated Sn‐Pb thickness saturated above the limiting current density. The optimal conditions for solder bump fabrication were found at 6 A/dm² for 3 h in the case of Sn‐Pb bump plating and 6 A/dm² for 1 h for the Sn‐Ag bump plating. The bump shear strength for Sn‐Ag was found to be higher than that of Sn‐Pb.

To achieve good reliability and high performance flip chip interconnection, process parameters and materials used in the flip chip process must be optimised. In this paper reliability of Sn37Pb solder bumped flip chips on an FR5 board, using different fluxes and underfill materials, are tested in a temperature cycling test. Also the contact pad geometry used on the FR5 board had a great influence on the reliability of the joint. The solder bumps were grown on the well‐known TiW/Au under bump metallurgy (UBM1) with an extra layer of nickel (UBM2) which gives a reliable and high performance solder joint.

Au stud bump bonding technology is an effective means to realize heterogeneous integration of commercial chips in the 2.5D electronic packaging. The purpose of this paper is to study the long-term reliability of the Au stud bump treated by four different high temperature storage times (200°C for 0, 100, 200 and 300 h).

The bonding strength and the fracture behavior are investigated by chip shear test. The experiment is further studied by microstructural characterization approaches such as scanning electron microscope, energy dispersive spectrometer and so on.

It is recognized that there were mainly three typical fracture models during the chip shear test among all the Au stud bump samples treated by high temperature storage. For solder bump before aging, the fracture occurred at the interface between the Cu pad and the Au stud bump. As the aging time increased, the fracture mainly occurred inside the Au stud bump at 200°C for 100 and 200 h. When aging time increased to 300 h, it is found that the fracture transferred to the interface between the Au stud bump and the Al Pad.

In addition, the bonding strength also changed with the high temperature storage time increasing. The bonding strength does not change linearly with the high temperature storage time increasing but decreases first and then increases. The investigation shows that the formation of the intermetallic compounds because of the reaction between the Au and Al atoms plays a key role on the bonding strength and fracture behavior variation.

The dissolution processes and subsequent intermetallic reactions between high tin solder bump alloys and Cu‐ or Ni‐based UBM‐metallisations were investigated both theoretically and experimentally. The results showed that when the Cu UBM layer is used together with eutectic or higher Sn‐based solder alloys the dissolution of Cu and the rate of the Cu₆Sn₅ formation is too high for reliable interconnections. On the contrary, Ni provides feasible solution for UBM/high tin solder applications. Although there is strong chemical interaction between nickel and high Sn solder bump alloys, the dissolution and subsequent Ni₃Sn₄ layer growth rates are very low. Thus, a thin Ni layer can sustain interactions with high Sn liquid as well as solid solders during high temperature use. On the basis of the results obtained flip chip bonding with Ni‐based UBM structures provides a viable interconnection solution for reliable fine‐pitch applications.

The elimination of lead from solders for flip‐chip attachment has necessitated many new studies on the reliability of the resultant systems. There are many lead‐free solder material systems. However, most of them contain a large proportion of tin. The tin in the solder reacts with the copper layer present in some types of under bump metallisation (UBM) depleting the UBM of copper, and thereby causing loss of adhesion and a weak interface. In this work, the relative reliability of Cr/Cu/Cu and Cr/Cu/Cu/Ni UBM systems was studied. The UBM systems were deposited with an electroplated Sn‐3.5Ag lead‐free solder alloy. The results conclusively showed that the Cr/Cu/Cu/Ni UBM system is a better choice for the Sn‐3.5Ag lead‐free solder. In the Cr/Cu/Cu/Ni UBM system, the thickness of the nickel layer was found to be an important parameter. Multiple reflow and high temperature storage test results showed that serious depletion of the UBM layer could occur if the UBM layers were not optimised. The thermo‐mechanical reliability of Ni‐based UBM bumps showed promising results up to 1,500 temperature cycling.

Flip chip technology involves the attachment of active side of the silicon chip onto printed circuit board or substrate. The interconnections are provided by solder bumps, which are arranged in the area under the chip. Encapsulation helps reduce the impact of the thermal stress that results from the mismatch in the coefficient of thermal expansion between the silicon chip and the substrate. The adhesion of the encapsulant to the chip and the board coating are essential to the reliability of the package. This paper studies the adhesion characteristics of an encapsulant to a flip chip package. The quality of the encapsulation was inspected using a scanning acoustic microscope. The electrical continuity of the assemblies was tested during the liquid‐to‐liquid thermal shock testing. The various delamination mechanisms were then studied. Delamination was found predominantly at the interface between the passivation layer and the encapsulant material. Comparisons were made between samples assembled by different materials used, such as chip passivation layer, encapsulant materials, and fluxes. Finally, the best material combination was determined.

In the flip‐chip technology (FCT) used in current microelectronic packages, a Ni‐based under‐bump metallurgy (UBM) is widely used due to its slow reaction rate with Sn. In this study, solders joints of eutectic Pb‐Sn with a Ni UBM were employed to investigate the intermetallic compound (IMC) formation after aging at 150°C for various periods of time.

The compositions and elemental re‐distribution in the IMC formed due to the interfacial reaction between the Ni/Cu UBM and eutectic Sn‐Pb solders were evaluated with an electron probe microanalyzer. The interfacial morphologies were revealed with the aid of a field‐emission scanning electron microscope through a special etching technique.

At the centre of the chip side, two IMCs were found between the solder and Ni metallization. The scalloped‐like IMC was determined to be (Cu, Ni)₆Sn₅, while the nodule‐like IMC was (Ni,Cu)₃Sn₄. However, at the edge of the chip side, three IMCs were revealed. The scalloped‐like IMC was (Cu_1−y,Ni_y)₆Sn₅, the nodule‐like IMC was (Ni_1−x,Cu_x)₃Sn₄, and the layer‐type IMC was (Cu_1−z,Ni_z)₃Sn.

On the basis of the elemental distributions from the quantitative analysis of the IMC and the related phase transitions during the IMC formation, two distinct diffusion paths are proposed to illustrate the interfacial reaction and phase transformation between IMCs and solder in Sn‐Pb joints aged at 150°C. These diffusion paths demonstrated two kinds of phase equilibrium, including (Cu_1−z,Ni_z)₃Sn/(Cu_1−y,Ni_y)₆Sn₅/solder and (Ni_1−x,Cu_x)₃Sn₄/(Cu_1−yNi_y)₆Sn₅/solder.

A new solder‐bumped flip chip land grid array (LGA) chip scale package (CSP) called NuCSP is presented in this paper. NuCSP is a minimized body size package with a rigid substrate (interposer). The design concept is to utilize the interposer to redistribute the very fine pitch peripheral pads on the solder‐bumped chip to much larger pitch area‐array pads on the printed circuit board (PCB). Using conventional PCB substrate manufacturing processes, NuCSP offers a very low‐cost package suitable for memory chips and low pin‐count application‐specific ICs (ASICs). Also, NuCSP is surface mount technology (SMT) compatible and can be joined to the PCB with a 6‐mil (0.15mm) thick 63wt %Sn‐37% Pb solder paste.