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The purpose of this study is to propose a simplifying approach for modelling a reliability test. Modelling the reliability tests of printed circuit board (PCB)/microelectronic component assemblies requires the adoption of several simplifying assumptions. This study introduces and validates simplified assumptions for modeling a four-point bend test on a PCB/wafer-level chip scale packaging assembly.

In this study, simplifying assumptions were used. These involved substituting dynamic imposed displacement loading with an equivalent static loading, replacing the spherical shape of the interconnections with simplified shapes (cylindrical and cubic) and transitioning from a three-dimensional modelling approach to an equivalent two-dimensional model. The validity of these simplifications was confirmed through both quantitative and qualitative comparisons of the numerical results obtained. The maximum principal plastic strain in the solder balls and copper pads served as the criteria for comparison.

The simplified hypotheses were validated through quantitative and qualitative comparisons of the results from various models. Consequently, it was determined that the replacement of dynamic loading with equivalent static loading had no significant impact on the results. Similarly, substituting the spherical shape of interconnections with an equivalent shape and transitioning from a three-dimensional approach to a two-dimensional one did not substantially affect the precision of the obtained results.

This study serves as a valuable resource for researchers seeking to model accelerated reliability tests, particularly in the context of four-point bending tests. The results obtained in this study will assist other researchers in streamlining their numerical models, thereby reducing calculation costs through the utilization of the simplified hypotheses introduced and validated herein.

This study aims to replace current multi-layer and coplanar wire crossing methods in QCA technology to avoid fabrication difficulties caused by them.

Quantum-dot cellular automata (QCA) is one of the newly emerging nanoelectronics technology tools that is proposed as a good replacement for complementary metal oxide semiconductor (CMOS) technology. This technology has many challenges, among them being component interconnection and signal routing. This paper will propose a new wire crossing method to enhance layout use in a single layer. The presented method depends on the central cell clock phase to enable two signals to cross over without interference. QCADesigner software is used to simulate a full adder circuit designed with the proposed wire crossing method to be used as a benchmark for further analysis of the presented wire crossing approach. QCAPro software is used for power dissipation analysis of the proposed adder.

A new cost function is presented in this paper to draw attention to the fabrication difficulties of the technology when designing QCA circuits. This function is applied to the selected benchmark circuit, and the results show good performance of the proposed method compared to others. The improvement is around 59, 33 and 75% compared to the best reported multi-layer wire crossing, coplanar wire crossing and logical crossing, respectively. The power dissipation analysis shows that the proposed method does not cause any extra power consumption in the circuit.

In this paper, a new approach is developed to bypass the wire crossing problem in the QCA technique.

This study aims to improve the complexity of chaotic systems and the security accuracy of information encrypted transmission. Applying five-dimensional memristive Hopfield neural network (5D-HNN) to secure communication will greatly improve the confidentiality of signal transmission and greatly enhance the anticracking ability of the system.

Chaos masking: Chaos masking is the process of superimposing a message signal directly into a chaotic signal and masking the signal using the randomness of the chaotic output. Synchronous coupling: The coupled synchronization method first replicates the drive system to get the response system, and then adds the appropriate coupling term between the drive The synchronization error and the coupling term of the system will eventually converge to zero with time. The synchronization error and coupling term of the system will eventually converge to zero over time.

A 5D memristive neural network is obtained based on the original four-dimensional memristive neural network through the feedback control method. The system has five equations and contains infinite balance points. Compared with other systems, the 5D-HNN has rich dynamic behaviors, and the most unique feature is that it has multistable characteristics. First, its dissipation property, equilibrium point stability, bifurcation graph and Lyapunov exponent spectrum are analyzed to verify its chaotic state, and the system characteristics are more complex. Different dynamic characteristics can be obtained by adjusting the parameter k.

A new 5D memristive HNN is proposed and used in the secure communication

The purpose of this paper is to introduce an innovative theoretical, numerical and experimental investigations on the HP NGD function. The identified HP NGD topology under study is constituted by first order passive RC-network. The simulations and measurements confirm in very good agreement the HP NGD behaviors of the tested circuits. NGD responses with optimal values of about -1 ns and cut-off frequencies of about 20 MHz are obtained.

The identified HP NGD topology understudy is constituted by a first-order passive Resistor-capacitor RC network. An innovative approach to HP NGD analysis is developed. The analytical investigation from the voltage transfer function showing the meaning of HP properties is established.

This paper introduces innovative theoretical, numerical and experimental investigations on the HP NGD function.

The NGD characterization as a function of the resistance and capacitance parameters is investigated. The feasibility of the HP NGD function is verified with proofs of concept constituted of lumped surface mounted components on printed circuit boards. The simulations and measurements confirm in very good agreement the HP NGD behaviors of the tested circuits. NGD responses with optimal values of about −1 ns and cut-off frequencies of about 20 MHz are obtained.

The purpose of this research paper is to explore the possibility to enhance the power transfer from piezoelectric energy harvester (PEH) source to the load. As the proposed gyrator-induced voltage flip technique (GIVFT) does not require bulky components such as physical inductors, it is easily realizable in small integrated circuits (IC) package thereby offering performance benefits, reducing area overhead and providing cost benefits for constrained self-powered autonomous Internet-of-Things (IoT) applications.

This paper presents an inductorless interface circuit for PEH. The proposed technique is called GIVFT and is demonstrated using active elements. The authors use gyrator to induce voltage flip at the output side of PEH to enhance the charge extraction from PEH. The proposed technique uses the current-voltage (I-V) relationship of gyrator to get appropriate phasor response necessary to induce the voltage flip at the output of PEH to gain power transfer enhancement at the load.

The experimental results show the efficacy of the GIVFT realization for enhanced power extraction. The authors have compared their proposed design with popular earlier reported interface circuits. Experimentally measured performance improvement is 1.86×higher than the baseline comparison of full-wave bridge rectifier circuit. The authors demonstrated a voltage flip using GIVFT to gain power transfer improvement in piezoelectric energy harvesting.

To the best of the authors’ knowledge, pertaining to the field of PEH, this is the first reported GIVFT based on the I-V relationship of the gyrator. The proposed approach could be useful for constrained self-powered autonomous IoT applications, and it could be of importance in guiding the design of new interface circuits for PEH.

The purpose of this paper is to study, a bridged-T topology with inductorless passive network used as a bandpass (BP) negative group delay (NGD) function.

The BP NGD topology under study is composed of an inductorless passive resistive capacitive network. The circuit analysis is elaborated from the equivalent impedance matrix. Then, the analytical model of the C-shunt bridged-T topology voltage transfer function is established. The BP NGD analysis of the considered topology is developed in function of the bridged-T parameters. The NGD properties and characterizations of the proposed topology are analytically expressed. Moreover, the relevance of the BP NGD theory is verified with the design and fabrication of surface mounted device components-based proof-of-concept (PoC).

From measurement results, the BP NGD network with −151 ns at the center frequency of 1 MHz over −6.6 dB attenuation is in very good agreement with the C-shunt bridged-T PoC.

This paper develops a mathematical modeling theory and measurement of a C-shunt bridged-T network circuit.

Full adder cells are building blocks of arithmetic circuits and affect the performance of the entire digital system. The purpose of this study is to provide a low-power and high-performance full adder cell.

Approximate computing is a novel paradigm that is used to design low-power and high-performance circuits. In this paper, a novel 1-bit approximate full adder cell is presented using the combination of complementary metal-oxide-semiconductor, transmission gate and pass transistor logic styles.

Simulation results confirm the superiority of the proposed design in terms of power consumption and power–delay product (PDP) criteria compared to state-of-the-art circuits. Also, the proposed full adder cell is applied in an 8-bit ripple carry adder to accomplish image processing applications including image blending, motion detection and edge detection. The results confirm that the proposed cell has premier compromise and outperforms its counterparts.

The proposed cell consists of only 11 transistors and decreases the switching activity remarkably. Therefore, it is a low-power and low-PDP cell.

As it is known, the electrostatic discharge (ESD) protection design of integrated circuit is very important, among which the silicon controlled rectifier (SCR) is one of the most commonly used ESD protection devices. However, the traditional SCR has the disadvantages of too high trigger voltage, too low holding voltage after the snapback and longer turn-on time. The purpose of this paper is to design a high-performance SCR in accordance with the design window under 0.25 µm process, and provide a new scheme for SCR design to reduce the trigger voltage, improve the holding voltage and reduce the turn-on time.

Based on the traditional SCR, an RC-INV trigger circuit is introduced. Through theoretical analysis, TCAD simulation and tape-out verification, it is shown that RC-INV triggering SCR can reduce the trigger voltage, increase the holding voltage and reduce the turn-on time of the device on the premise of maintaining good robustness.

The RC-INV triggering SCR has great performance, and the test shows that the transmission line pulse curve with almost no snapback can be obtained. Compared with the traditional SCR, the trigger voltage decreased from 32.39 to 16.24 V, the holding voltage increased from 3.12 to 14.18 V and the turn-on time decreased from 29.6 to 16.6 ns, decreasing by 43.9% the level of human body model reached 18 kV+.

Under 0.25 µm BCD process, this study propose a high-performance RC-INV triggering SCR ESD protection device. The work presented in this paper has a certain guiding significance for the design of SCR ESD protection devices.

This paper aims to propose a semianalytical model of a squirrel-cage induction machine (SCIM), considering local magnetic saturation and eddy-currents induced in the rotor bars.

The regions of the rotor and stator are divided into elementary subdomains (E-SDs) characterized by general solutions at the first harmonic of the magneto-harmonic Maxwell’s equations. These E-SDs are connected in both directions (i.e., along the r- and θ-edges).

The calculation of the magnetic field has been validated for various values of slip and iron permeability. All electromagnetic quantities were compared with those obtained using a two-dimensional finite-element method. The semianalytical results are satisfactory compared with the numerical results, considering both the amplitude and waveform.

Expansion of the recent analytical model (E-SD technique) for the full prediction of the magnetic field in SCIMs, considering the local saturation effect and the eddy-currents induced in the rotor bars.

An excessive increase in temperature will reduce the lifespan and even burn the coil. The variety of materials in the structure of the electromagnet along with its multi-layer winding creates a complex and heterogeneous thermal structure. There are very few researches that are completely focused on the thermal analysis of electromagnets. The purpose of this paper is to provide an accurate, yet fast and simple method for the thermal analysis of cylindrical electromagnets in both transient and steady-state modes. For this purpose, a thermal equivalent circuit (TEC) is presented based on the nodding approach.

The results of TEC analysis of cylindrical electromagnet, for two orthogonal and orthocyclic winding coil technologies, were compared with the results of the thermal simulation in COMSOL. The authors also built a laboratory model of the cylindrical electromagnet, similar to those analyzed and simulated, and measured the temperature in different parts of it.

The comparison of the results obtained from different methods for the thermal analysis of the cylindrical electromagnet indicates that the proposed TEC has an error of less than 2%. The simplicity and high accuracy of the results are the most important advantages of the proposed TEC.

Comparing the information and results related to winding schemes, indicates that the orthogonal winding has less cost and weight due to the shorter length of the wire used. On the other hand, orthocyclic winding generates lower temperature and has more lifting force, and is simpler to implement. Therefore, in practice, orthocyclic winding technology is usually used.