This paper sets out to design and realize a highly linear, wide dynamic range and high switching efficiency integrated CMOS up‐conversion mixer for two‐step IEEE 802.1a…
This paper sets out to design and realize a highly linear, wide dynamic range and high switching efficiency integrated CMOS up‐conversion mixer for two‐step IEEE 802.1a WLAN transmitter application in 0.18‐μm deep submicron CMOS technology.
A folded current draining low‐voltage mixer architecture is explored and an extensive simulation carried out utilizing Cadence Spectre‐RF tool in optimizing the linearity, input third‐order intercept point (IIP3), the dynamic range, 1 dB compression point (P−1dB), power dissipation and reduction of switching quad Cgs, input gate‐source capacitance, in enhancing the switching efficiency of the proposed architecture.
A highly linear, high input dynamic range, low voltage folded up‐conversion mixer architecture is realized in a significant comparable performance with respect to conventional reported architecture, indicating −8.87 dBm of OIP3 corresponding to 15.27 dBm IIP3 and 4.37 dBm of P−1dB in 0.18‐μm CMOS technology.
The optimized mixer architecture is stringent to an up‐converter application. To be utilized as a down converter at the receiver end, parameters, namely as noise figure and conversion gain, are of additional importance.
The designed folded mixer architecture is in need of integration to a two‐step up‐conversion transmitter architecture which relaxes the injection pulling effect for a given low voltage headroom, with low power dissipation design.
In this work, an integrated folded architecture with on‐chip process, voltage and temperature compensated biasing circuit is explored and enhanced, raising awareness of adapting improved multiplier blocks in achieving optimal performance in WLAN transceiver architecture.
The purpose of this paper is to design and realize a low‐phase noise, high‐output power, and high‐tuning range, fully integrated source injection parallel coupled…
The purpose of this paper is to design and realize a low‐phase noise, high‐output power, and high‐tuning range, fully integrated source injection parallel coupled (SIPC)‐based inductor‐capacitor (LC)‐quadrature voltage controlled oscillator (QVCO) covering WiMAX frequency range in 0.18‐μm deep submicron CMOS technology.
A pMOS based‐SIPC LC‐QVCO topology is realized with the center frequency of 2.58 GHz. On chip spiral inductor is integrated with substantial quality factor, Q coupled with underlying pattern ground shield (PGS) shielding. An enhanced tuning range is achieved by integrating the diode connected MOS‐based varactors. The CMOS‐based autonomous SIPC LC‐QVCO circuit was characterized for its output phase noise, tuning range and power spectrum response via wafer probing, utilizing a signal source analyzer (Agilent E5052 A).
A quadrature oscillator catering to the needs of local oscillator (LO) generation covering the frequency range of WiMAX is realized. The parallel coupled architecture adapts direct source coupling, bypassing the LC resonator tank and relaxes the close in phase noise up‐conversion. The design consumes 2.19 mm2 of active chip area and measures a phase noise of −114.34 dBc/Hz at 1 MHz of offset frequency with 2.67 GHz of output frequency at 0.9 V of input tuning voltage. The corresponding output power measures to be −10.1 dBm, well suited for mixer hard switching. The design is realized in one poly, six metal 0.18‐μm standard CMOS technology.
Owing to convergence discrepancy in the analysis, a diode‐connected MOS varactor is adapted in contrary to the accumulation mode MOS varactors with superior tuning range.
The designed SIPC LC‐QVCO is of need in the generation of low‐phase noise, highly matched quadrature LO generation covering the WiMAX frequency range. The adapted parallel coupling also relaxes the voltage headroom limitation.
This paper shows how a fully integrated CMOS‐based SIPC LC‐QVCO architecture is adapted with low‐output phase noise and low voltage headroom consumption covering the WiMAX frequency range.