Search results

This paper aims to find a closed-form expression for the frequency and amplitude of single-ended ring oscillators when transistors experience all regions.

In this paper, the analytical relationships presented for ring oscillator amplitude and frequency are approximately derived due to the nonlinear nature of this oscillator, taking into account the differential equation that governs the ring oscillator and its output waveform.

In the case where the transistors experience the cut-off region, the relationships presented so far have no connection between the frequency and the dimensions of the transistor, which is not valid in practice. The relationship is presented for the frequency, including the dimensions of the transistor. Also, a simple and approximately accurate relationship for the oscillator amplitude is provided in this case.

The validity of these relationships has been investigated by analyzing and simulating a single-ended oscillator in 0.18 µm technology.

Full adder cells are building blocks of arithmetic circuits and affect the performance of the entire digital system. The purpose of this study is to provide a low-power and high-performance full adder cell.

Approximate computing is a novel paradigm that is used to design low-power and high-performance circuits. In this paper, a novel 1-bit approximate full adder cell is presented using the combination of complementary metal-oxide-semiconductor, transmission gate and pass transistor logic styles.

Simulation results confirm the superiority of the proposed design in terms of power consumption and power–delay product (PDP) criteria compared to state-of-the-art circuits. Also, the proposed full adder cell is applied in an 8-bit ripple carry adder to accomplish image processing applications including image blending, motion detection and edge detection. The results confirm that the proposed cell has premier compromise and outperforms its counterparts.

The proposed cell consists of only 11 transistors and decreases the switching activity remarkably. Therefore, it is a low-power and low-PDP cell.

The purpose of this paper is to find a closed relation for the phase noise of LC oscillators.

The governing equation of oscillators is generally a stochastic nonlinear differential equation. In this paper, a closed relation for the phase noise of LC oscillators was obtained by approximating the I–V characteristic of the oscillator with third-degree polynomials and analyzing its differential equation.

This relation expresses phase noise directly in terms of circuit parameters, including the sizes of the transistors and the bias. Next, for evaluation, the phase noise of the cross-coupled oscillator without tail current was calculated with the proposed model. In this approach, the obtained equations are expressed independently of technology by combining the obtained phase noise relation and g_m/I_D method.

A technology-independent method using the g_m/I_D method and the closed relationship is provided to calculate phase noise.

The purpose of this study is to show that due to the emergence of the Internet of Things (IoT) industry in recent years, the demand for the higher integration of wireless communication systems with a higher data rate of transmission capacity and lower power consumption has increased tremendously. The radio frequency power amplifier (PA) design is getting more challenging and crucial. A PA for a 2.45 GHz IoT application using 0.18 µm complementary metal oxide semiconductor (CMOS) technology is presented in this paper.

The design consists of two stages, the driver and output stage, where both use a single-stage common source transistor configuration. In view of performance, the PA can deliver more than 20 dB gain from 2.4 GHz to 2.5 GHz.

The maximum output power achieved by PA is 13.28 dBm. As the PA design is targeted for Bluetooth low energy (BLE) transmitter use, a minimum of 10 dBm output power should be achieved by PA to transmit the signal in BLE standard. The PA exhibits a constant output third-order interception point of 18 dBm before PA becomes saturated after 10 dBm output power. The PA shows a peak power added efficiency of 17.82% at the 13.24 dBm output power.

The PA design exhibits good linearity up to 10 dBm out the PA design exhibits good linearity up to 10 dBm output power without sacrificing efficiency. At the operating frequency of 2.45 GHz, the PA exhibits a stability k-factor, the value of more than 1; thus, the PA design is considered unconditional stable. Besides, the PA shows the s-parameters performance of –7.91 dB for S11, –11.07 dB for S22 and 21.5 dB for S21.

The purpose of this paper is to design novel tunnel field effect transistor (TFET) using graphene nanoribbons (GNRs).

To design the proposed TFET, the bilayer GNRs (BLGNRs) have been used as the channel material. The BLGNR-TFET is designed in QuantumATK, depending on 2-D Poisson’s equation and non-equilibrium Green’s function (NEGF) formalism.

The performance of the proposed BLGNR-TFET is investigated in terms of current and voltage (I-V) characteristics and transconductance. Moreover, the proposed device performance is compared with the monolayer GNR-TFET (MLGNR-TFET). From the simulation results, it is investigated that the BLGNR-TFET shows high current and gain over the MLGNR-TFET.

This paper presents a new technique to design GNR-based TFET for future low power very large-scale integration (VLSI) devices.

The purpose of chopper amplifier is to provide the wideband frequency to support biomedical signals.

This paper proposes a chopper-stabilized amplifier with a cascoded operational transconductance amplifier. The high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor.

The total power consumption is 451 nW with a supplied voltage of 800 mV. The Gain and common mode rejection ratio are 48 dB and 78 dB, respectively.

All kinds of real time data analysis was not carried out, only few test samples related to EEG signals are validated because the real time chip was not manufactured due to funding issues.

The proposed work was validated with Monte-Carlo simulations. There is no external funding for the proposed work. So there is no fabrication for the design. But post simulations are performed.

The high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor. To the best of the author’s knowledge, this concept is completely novel and there are no publications on this work. All the modules designed for chopper amplifier are new concepts.

The purpose of this paper is to design multiplexers (MUXs) based on ternary half subtractor and full subtractor using carbon nanotube field-effect transistors.

Conventionally, the binary logic functions are developed by using the binary decision diagram (BDD) systems. Each node in BDD is replaced by 2:1 MUX to implement the digital circuits. Similarly, in the ternary decision diagram, each node has to be replaced by 3:1 MUX. In this paper, ternary transformed BDD is used to design the ternary subtractors using 2:1 MUXs.

The performance of the proposed ternary half subtractor and full subtractor using the 2:1 MUX are compared with the 3:1 MUX-based ternary circuits. It has been observed that the delay, power and power delay product values are reduced, respectively, by 67.6%, 84.3%, 94.9% for half subtractor and 67.7%, 70.1%, 90.3% for full subtractor. From the Monte Carlo simulations, it is observed that the propagation delay and power dissipation of the proposed subtractors are increased by increasing the channel length due to process variations. The stability test is also performed and observed that the stability increases as the channel length and diameter are increased.

The proposed half subtractor and full subtractor show better performance over the existing subtractors.

The design and implementation of a broadband quasi-monolithic microwave integrated circuit (q-MMIC) power amplifier (PA) is presented for 0.2 to 2.2 GHz applications.

To obtain an efficient, high-gain and high-power performance with in a compact and low-cost size, the prototype is based on Gallium nitride (GaN) on SiC 0.25-µm transistors, whereas the passive matching networks are realized on an AlN substrate as thin film circuit.

Measured results of the q-MMIC PA across the 0.2 to 2.2 GHz band show at least 32 ± 3 dB small-signal gains, an output power of 7 to 12 W and an average power add efficiency greater than 54%. The q-MMIC occupies an area of 12.8 × 14.5 mm².

To the best of the authors’ knowledge, this work reports the first full integrated PA which covers the frequency range of 0.2 to 2.2 GHz and achieves the combination of highest gain, about 10 W output power, together with the smallest component size among all published GaN PAs to date.

As it is known, the electrostatic discharge (ESD) protection design of integrated circuit is very important, among which the silicon controlled rectifier (SCR) is one of the most commonly used ESD protection devices. However, the traditional SCR has the disadvantages of too high trigger voltage, too low holding voltage after the snapback and longer turn-on time. The purpose of this paper is to design a high-performance SCR in accordance with the design window under 0.25 µm process, and provide a new scheme for SCR design to reduce the trigger voltage, improve the holding voltage and reduce the turn-on time.

Based on the traditional SCR, an RC-INV trigger circuit is introduced. Through theoretical analysis, TCAD simulation and tape-out verification, it is shown that RC-INV triggering SCR can reduce the trigger voltage, increase the holding voltage and reduce the turn-on time of the device on the premise of maintaining good robustness.

The RC-INV triggering SCR has great performance, and the test shows that the transmission line pulse curve with almost no snapback can be obtained. Compared with the traditional SCR, the trigger voltage decreased from 32.39 to 16.24 V, the holding voltage increased from 3.12 to 14.18 V and the turn-on time decreased from 29.6 to 16.6 ns, decreasing by 43.9% the level of human body model reached 18 kV+.

Under 0.25 µm BCD process, this study propose a high-performance RC-INV triggering SCR ESD protection device. The work presented in this paper has a certain guiding significance for the design of SCR ESD protection devices.

The purpose of this paper is to prevent the destruction of other parts of a wind energy conversion system because of faults, the diagnosis of insulated-gate bipolar transistor (IGBT) faults has become an essential topic of study. Demand for sustainable energy sources has been prompted by rising environmental pollution and energy requirements. Renewable energy has been identified as a viable substitute for conventional fossil fuel energy generation. Because of its rapid installation time and adaptable expenditure for construction scale, wind energy has emerged as a great energy resource. Power converter failure is particularly significant for the reliable operation of wind power conversion systems because it not only has a high yearly fault rate but also a prolonged downtime. The power converters will continue to operate even after the failure, especially the open-circuit fault, endangering their other parts and impairing their functionality.

The most widely used signal processing methods for locating open-switch faults in power devices are the short-time Fourier transform and wavelet transform (WT) – based on time–frequency analysis. To increase their effectiveness, these methods necessitate the intensive use of computational resources. This study suggests a fault detection technique using empirical mode decomposition (EMD) that examines the phase currents from a power inverter. Furthermore, the intrinsic mode function’s relative energy entropy (REE) and simple logical operations are used to locate IGBT open switch failures.

The presented scheme successfully locates and detects 21 various classes of IGBT faults that could arise in a two-level three-phase voltage source inverter (VSI). To verify the efficacy of the proposed fault diagnosis (FD) scheme, the test is performed under various operating conditions of the power converter and induction motor load. The proposed method outperforms existing FD schemes in the literature in terms of fault coverage and robustness.

This study introduces an EMD–IMF–REE-based FD method for VSIs in wind turbine systems, which enhances the effectiveness and robustness of the FD method.