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Article
Publication date: 5 October 2022

Alok Kumar Mishra, Urvashi Chopra, Vaithiyanathan D. and Baljit Kaur

A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital…

Abstract

Purpose

A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops.

Design/methodology/approach

This paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops.

Findings

The proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop.

Originality/value

This work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.

Details

Circuit World, vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 15 September 2022

Parul Trivedi and B.B. Tiwari

The primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is…

Abstract

Purpose

The primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is less sensitive to power supply variations. In a few decades, with the advancement of modern wireless communication equipment, there has been an increasing demand for low-power and robust communication systems for longer battery life. A sudden drop in power significantly affects the performance of the VCO. Supply insensitive circuit design is the backbone of uninterrupted VCO performance. Because of their important roles in a variety of applications, VCOs and phase locked loops (PLLs) have been the subject of significant research for decades. For a few decades, the VCO has been one of the major components used to provide a local frequency signal to the PLL.

Design/methodology/approach

First, this paper chose to present recent developments on implemented techniques of ring VCO design for various applications. A complementary metal oxide semiconductor (CMOS)-based supply compensation technique is presented, which aims to reduce the change in oscillation frequency with the supply. The proposed circuit is designed and simulated on Cadence Virtuoso in 0.18 µm CMOS process under 1.8 V power supply. Active differential configuration with a cross-coupled NMOS structure is designed, which eliminates losses and negates supply noise. The proposed VCO is designed for excellent performance in many areas, including the L-band microwave frequency range, supply sensitivity, occupied area, power consumption and phase noise.

Findings

This work provides the complete design aspect of a novel ring VCO design for the L-band frequency range, low phase noise, low occupied area and low power applications. The maximum value of the supply sensitivity for the proposed ring VCO is 1.31, which is achieved by changing the VDD by ±0.5%. A tuning frequency range of 1.47–1.81 GHz is achieved, which falls within the L-band frequency range. This frequency range is achieved by varying the control voltage from 0.0 to 0.8 V, which shows that the proposed ring VCO is also suitable for low voltage regions. The total power consumed by the proposed ring VCO is 14.70 mW, a remarkably low value using this large transistor count. The achievable value of phase noise is −88.76 dBc/Hz @ 1 MHz offset frequency, which is a relatively small value. The performance of the proposed ring VCO is also evaluated by the figure of merit, achieving −163.13 dBc/Hz, which assures the specificity of the proposed design. The process and temperature variation simulations also validate the proposed design. The proposed oscillator occupied an extremely small area of only 0.00019 mm2 compared to contemporary designs.

Originality/value

The proposed CMOS-based supply compensation method is a unique design with the size and other parameters of the components used. All the data and results obtained show its originality in comparison with other designs. The obtained results are preserved to the fullest extent.

Details

Circuit World, vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 24 August 2021

Kumar Neeraj and Jitendra Kumar Das

High throughput and power efficient computing devices are highly essential in many autonomous system-based applications. Since the computational power keeps on increasing in…

Abstract

Purpose

High throughput and power efficient computing devices are highly essential in many autonomous system-based applications. Since the computational power keeps on increasing in recent years, it is necessary to develop energy efficient static RAM (SRAM) memories with high speed. Nowadays, Static Random-Access Memory cells are predominantly liable to soft errors due to the serious charge which is crucial to trouble a cell because of fewer noise margins, short supply voltages and lesser node capacitances.

Design/methodology/approach

Power efficient SRAM design is a major task for improving computing abilities of autonomous systems. In this research, instability is considered as a major issue present in the design of SRAM. Therefore, to eliminate soft errors and balance leakage instability problems, a signal noise margin (SNM) through the level shifter circuit is proposed.

Findings

Bias Temperature Instabilities (BTI) are considered as the primary technology for recently combined devices to reduce degradation. The proposed level shifter-based 6T SRAM achieves better results in terms of delay, power and SNM when compared with existing 6T devices and this 6T SRAM-BTI with 7 nm technology is also applicable for low power portable healthcare applications. In biomedical applications, Body Area Networks (BANs) require the power-efficient SRAM design to extend the battery life of BAN sensor nodes.

Originality/value

The proposed method focuses on high speed and power efficient SRAM design for smart ubiquitous sensors. The effect of BTI is almost eliminated in the proposed design.

Details

International Journal of Intelligent Unmanned Systems, vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 2049-6427

Keywords

Article
Publication date: 13 September 2021

Naresh Kattekola, Amol Jawale, Pallab Kumar Nath and Shubhankar Majumdar

This paper aims to improve the performance of approximate multiplier in terms of peak signal to noise ratio (PSNR) and quality of the image.

Abstract

Purpose

This paper aims to improve the performance of approximate multiplier in terms of peak signal to noise ratio (PSNR) and quality of the image.

Design/methodology/approach

The paper proposes an approximate circuit for 4:2 compressor, which shows a significant amount of improvement in performance metrics than that of the existing designs. This paper also reports a hybrid architecture for the Dadda multiplier, which incorporates proposed 4:2 compressor circuit as a basic building block.

Findings

Hybrid Dadda multiplier architecture is used in a median filter for image de-noising application and achieved 20% more PSNR than that of the best available designs.

Originality/value

The proposed 4:2 compressor improves the error metrics of a Hybrid Dadda multiplier.

Details

Circuit World, vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 25 February 2021

Sudipta Ghosh, P. Venkateswaran and Subir Kumar Sarkar

High packaging density in the present VLSI era builds an acute power crisis, which limits the use of MOSFET device as a constituent block in CMOS technology. This leads…

Abstract

Purpose

High packaging density in the present VLSI era builds an acute power crisis, which limits the use of MOSFET device as a constituent block in CMOS technology. This leads researchers in looking for alternative devices, which can replace the MOSFET in CMOS VLSI logic design. In a quest for alternative devices, tunnel field effect transistor emerged as a potential alternative in recent times. The purpose of this study is to enhance the performances of the proposed device structure and make it compatible with circuit implementation. Finally, the performances of that circuit are compared with CMOS circuit and a comparative study is made to find the superiority of the proposed circuit with respect to conventional CMOS circuit.

Design/methodology/approach

Silicon–germanium heterostructure is currently one of the most promising architectures for semiconductor devices such as tunnel field effect transistor. Analytical modeling is computed and programmed with MATLAB software. Two-dimensional device simulation is performed by using Silvaco TCAD (ATLAS). The modeled results are validated through the ATLAS simulation data. Therefore, an inverter circuit is implemented with the proposed device. The circuit is simulated with the Tanner EDA tool to evaluate its performances.

Findings

The proposed optimized device geometry delivers exceptionally low OFF current (order of 10^−18 A/um), fairly high ON current (5x10^−5 A/um) and a steep subthreshold slope (20 mV/decade) followed by excellent ON–OFF current ratio (order of 10^13) compared to the similar kind of heterostructures. With a very low threshold voltage, even lesser than 0.1 V, the proposed device emerged as a good replacement of MOSFET in CMOS-like digital circuits. Hence, the device is implemented to construct a resistive inverter to study the circuit performances. The resistive inverter circuit is compared with a resistive CMOS inverter circuit. Both the circuit performances are analyzed and compared in terms of power dissipation, propagation delay and power-delay product. The outcomes of the experiments prove that the performance matrices of heterojunction Tunnel FET (HTFET)-based inverter are way ahead of that of CMOS-based inverter.

Originality/value

Germanium–silicon HTFET with stack gate oxide is analytically modeled and optimized in terms of performance matrices. The device performances are appreciable in comparison with the device structures published in contemporary literature. CMOS-like resistive inverter circuit, implemented with this proposed device, performs well and outruns the circuit performances of the conventional CMOS circuit at 45-nm technological node.

Details

Circuit World, vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 21 September 2022

Wanjun Yin and Lin-na Jiang

The purpose of this paper through the redundant monitoring unit reflecting the real-time temperature change of the array, an adaptive refresh circuit based on temperature is…

Abstract

Purpose

The purpose of this paper through the redundant monitoring unit reflecting the real-time temperature change of the array, an adaptive refresh circuit based on temperature is designed.

Design/methodology/approach

This paper proposed a circuit design for temperature-adaptive refresh with a fixed refresh frequency of traditional memory, high refresh power consumption at low temperature and low refresh frequency at high temperature.

Findings

Adding a metal oxide semiconductor (MOS) redundancy monitoring unit consistent with the storage unit to the storage bank can monitor the temperature change of the storage bank in real time, so that temperature-based memory adaptive refresh can be implemented.

Originality/value

According to the characteristics that the data holding time of dynamic random access memory storage unit decreases with the increase of temperature, a MOS redundant monitoring unit which is consistent with the storage unit is added to the storage array with the 2T storage unit as the core.

Details

Circuit World, vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 1 July 2021

Subhrapratim Nath, Jamuna Kanta Sing and Subir Kumar Sarkar

Advancement in optimization of VLSI circuits involves reduction in chip size from micrometer to nanometer level as well as fabrication of a billions of transistors in a single die…

Abstract

Purpose

Advancement in optimization of VLSI circuits involves reduction in chip size from micrometer to nanometer level as well as fabrication of a billions of transistors in a single die where global routing problem remains significant with a trade-off of power dissipation and interconnect delay. This paper aims to solve the increased complexity in VLSI chip by minimization of the wire length in VLSI circuits using a new approach based on nature-inspired meta-heuristic, invasive weed optimization (IWO). Further, this paper aims to achieve maximum circuit optimization using IWO hybridized with particle swarm optimization (PSO).

Design/methodology/approach

This paper projects the complexities of global routing process of VLSI circuit design in mapping it with a well-known NP-complete problem, the minimum rectilinear Steiner tree (MRST) problem. IWO meta-heuristic algorithm is proposed to meet the MRST problem more efficiently and thereby reducing the overall wire-length of interconnected nodes. Further, the proposed approach is hybridized with PSO, and a comparative analysis is performed with geosteiner 5.0.1 and existing PSO technique over minimization, consistency and convergence against available benchmark.

Findings

This paper provides high performance–enhanced IWO algorithm, which keeps in generating low MRST value, thereby successful wire length reduction of VLSI circuits is significantly achieved as evident from the experimental results as compared to PSO algorithm and also generates value nearer to geosteiner 5.0.1 benchmark. Even with big VLSI instances, hybrid IWO with PSO establishes its robustness over achieving improved optimization of overall wire length of VLSI circuits.

Practical implications

This paper includes implications in the areas of optimization of VLSI circuit design specifically in the arena of VLSI routing and the recent developments in routing optimization using meta-heuristic algorithms.

Originality/value

This paper fulfills an identified need to study optimization of VLSI circuits where minimization of overall interconnected wire length in global routing plays a significant role. Use of nature-based meta-heuristics in solving the global routing problem is projected to be an alternative approach other than conventional method.

Details

Circuit World, vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 16 June 2021

Kulbhushan Sharma, Anisha Pathania, Jaya Madan, Rahul Pandey and Rajnish Sharma

Adoption of integrated MOS based pseudo-resistor (PR) structures instead of using off-chip passive poly resistors for analog circuits in complementary metal oxide semiconductor…

Abstract

Purpose

Adoption of integrated MOS based pseudo-resistor (PR) structures instead of using off-chip passive poly resistors for analog circuits in complementary metal oxide semiconductor technology (CMOS) is an area-efficient way for realizing larger time constants. However, issue of common-mode voltage shifting and excess dependency on the process and temperature variations introduce nonlinearity in such structures. So there is dire need to not only closely look for the origin of the problem with the help of a thorough mathematical analysis but also suggest the most suitable PR structure for the purpose catering broadly to biomedical analog circuit applications.

Design/methodology/approach

In this work, incremental resistance (IR) expressions and IR range for balanced PR (BPR) structures operating in the subthreshold region have been closely analyzed for broader range of process-voltage-temperature variations. All the post-layout simulations have been obtained using BSIM3V3 device models in 0.18 µm standard CMOS process.

Findings

The obtained results show that the pertinent problem of common-mode voltage shifting in such PR structures is completely resolved in scaled gate linearization and bulk-driven quasi-floating gate (BDQFG) BPR structures. Among all BPR structures, BDQFG BPR remarkably shows constant IR value of 1 TΩ over −1 V to 1 V voltage swing for wider process and temperature variations.

Research limitations/implications

Various balanced PR design techniques reported in this work will help the research community in implementing larger time constants for analog-mixed signal circuits.

Social implications

The PR design techniques presented in the present piece of work is expected to be used in developing tunable and accurate biomedical prosthetics.

Originality/value

The BPR structures thoroughly analyzed and reported in this work may be useful in the design of analog circuits specifically for applications such as neural signal recording, cardiac electrical impedance tomography and other low-frequency biomedical applications.

Details

Circuit World, vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 0305-6120

Keywords

Open Access
Article
Publication date: 28 March 2024

Elgazzar Iman Mahmoud Khalil

At the beginning of the 21st century, a new class of information workers, the “information have-less” has risen. This class of workers alleviates the influence of information and…

Abstract

Purpose

At the beginning of the 21st century, a new class of information workers, the “information have-less” has risen. This class of workers alleviates the influence of information and communication technologies (ICTs) revolution on poverty and unemployment. The purpose of this study is to investigate the presence of this class of workers in Egypt and assess the size and potential growth of this category of workers.

Design/methodology/approach

The study clarifies the conceptual framework of the new division of labor, in the information age. The Central Agency for Public Mobilization and Statistics, American Chamber of Commerce in Egypt, Ministry of Communications and Information Technology and Information and Decision Support Center websites provided secondary data for this study. These data are used to assess the size of “the information have less” in Egypt.

Findings

The division of work and class, in the 21st century, depends on the level of skills possessed to work with ICTs. So, class and labor nowadays could be divided into self-programmable labor (Innovators). Information have-less labor class, adding value to the economy by learning skills and presenting repetitive work. Generic labor class, who cannot work with ICTs, and work in jobs, that do not need computers or other ICTs. The study has shown that the “information have-less” labor class is present in Egypt since the beginning of the 21st century, in all its categories; entrepreneurism, the service sector and the manufacturing sector. There are approximately 50% of this labor class in the service sector and only 13% of the information have-less works in manufacturing sector despite the great opportunities that Egypt has to expand manufacturing to absorb more employment. The inclusion of information technology (IT), in all domains, has not decreased employment in Western countries but has reallocated information have-less employment toward the service sector, and there would probably be the same effect in Egypt.

Practical implications

The study highlights the need for Egyptian policymakers to encourage the manufacturing and service sectors to provide huge working opportunities. The Egyptian government has to change the educational policies, at all stages, to include digital learning skills so IT can be incorporated in a wide range of economic activities. Further research includes: conducting a survey to measure the contribution of the entrepreneurial part of the information have-less employment in Egypt. In addition, a model may be developed, by the researcher to examine the reallocation of employees in Egypt.

Originality/value

Studying employment, in Egypt, using the conceptual framework of the information age is rarely being done.

Details

Review of Economics and Political Science, vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 2356-9980

Keywords

Article
Publication date: 6 March 2024

Mouna Zerzeri, Intissar Moussa and Adel Khedher

The purpose of this paper aims to design a robust wind turbine emulator (WTE) based on a three-phase induction motor (3PIM).

Abstract

Purpose

The purpose of this paper aims to design a robust wind turbine emulator (WTE) based on a three-phase induction motor (3PIM).

Design/methodology/approach

The 3PIM is driven by a soft voltage source inverter (VSI) controlled by a specific space vector modulation. By adjusting the appropriate vector sequence selection, the desired VSI output voltage allows a real wind turbine speed emulation in the laboratory, taking into account the wind profile, static and dynamic behaviors and parametric variations for theoretical and then experimental analysis. A Mexican hat profile and a sinusoidal profile are therefore used as the wind speed system input to highlight the electrical, mechanical and electromagnetic system response.

Findings

The simulation results, based on relative error data, show that the proposed reactive power control method effectively estimates the flux and the rotor time constant, thus ensuring an accurate trajectory tracking of the wind speed for the wind emulation application.

Originality/value

The proposed architecture achieves its results through the use of mathematical theory and WTE topology combine with an online adaptive estimator and Lyapunov stability adaptation control methods. These approaches are particularly relevant for low-cost or low-power alternative current (AC) motor drives in the field of renewable energy emulation. It has the advantage of eliminating the need for expensive and unreliable position transducers, thereby increasing the emulator drive life. A comparative analysis was also carried out to highlight the online adaptive estimator fast response time and accuracy.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering , vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 0332-1649

Keywords

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