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The purpose of this paper is to focus on through‐silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented.

This design addresses the electronic packaging of 3D IC integration with a passive TSV interposer for high‐power, high‐performance, high pin‐count, ultra fine‐pitch, small real‐estate, and low‐cost applications. To achieve this, the design uses chip‐to‐chip interconnections through a passive TSV interposer in a 3D IC integration system‐in‐package (SiP) format with excellent thermal management.

A generic, low‐cost and thermal‐enhanced 3D IC integration SiP with a passive interposer has been proposed for high‐performance applications. Also, the origin of 3D integration and the overview and outlook of 3D Si integration and 3D IC integration have been presented and discussed. Some important results and recommendations are summarized: the TSV/redistribution layer (RDL)/integrated passive devices passive interposer, which supports the high‐power chips on top and low‐power chips at its bottom, is the gut and workhorse of the current 3D IC integration design; with the passive interposer, it is not necessary to “dig” holes on the active chips. In fact, try to avoid making TSVs in the active chips; the passive interposer provides flexible coupling for whatever chips are available and/or necessary, and enhances the functionality and possibly the routings (shorter); with the passive interposer, the TSV manufacturing cost is lower because the requirement of TSV manufacturing yield is too high (>99.99 percent) for the active chips to bear additional costs due to TSV manufacturing yield loss; with the passive interposer, wafer thinning and thin‐wafer handling costs (for the interposer) are lower because these are not needed for the active chips and thus adds no cost due to yield loss; with the current designs, all the chips are bare; the packaging cost for individual chips is eliminated; more than 90 percent of heat from the 3D IC integration SiP is dissipated from the backside of high‐power chips using a thermal interface material and heat spreader/sink; the appearance and footprint of current 3D IC integration SiP designs are very attractive to integrated device manufactures, original equipment manufactures, and electronics manufacturing services (EMS) because they are standard packages; and underfills between the copper‐filled TSV interposer and the high‐ and low‐power chips are recommended to reduce creep damage of the lead‐free microbump solder joints and prolong their lives.

The paper's findings will be very useful to the electronic industry.

The purpose of this paper is to overview the effect of electroplating current wave forms on Cu filling of through‐silicon‐vias (TSV) for three‐dimensional (3D) packaging.

The paper takes the form of a literature review.

Effective TSV technology for 3D packaging involves various processes such as via formation, filling with conductive material, wafer thinning, and chip stacking. Among these processes, high‐speed via filling without defect is very important for applying the TSV process to industry with a lower production cost. In this paper, the effects of various current forms on Cu electroplating of TSV such as direct current (DC), pulse current (PC), pulse reverse current (PRC), and periodic pulse reverse current (PPR) are described in detail including recent studies.

TSV is a core technology for high density 3D packaging. This paper overviews the recent studies of various current forms on Cu‐filling of TSV.

A large-scale detection system with more data in short time bins, small dead space and small signal identification is the ideology the scientists pursuing. These proposed demands are able to be solved by 2.5 D integration. The substance of a 2.5 D integration is called silicon interposer, which consists of the through silicon via (TSV) and redistribution layer. However, the state-of-the-art silicon interposer is not able to sustain its own mechanical strength with the detector/readout array often sitting as standalone in large science facilities and fails to reduce the expansions on the installation of the components due to its insufficient thickness and size. This study aims to propose a moderation of current interposer with large-sized, standalone properties.

This paper proposes an interposer based on double-sided silicon vias (DSSVs) interconnection. Unlike conventional interposer that is interconnected by TSVs, DSSVs interposer is interconnected by top vias (T-vias) and bottom vias (B-vias).

The fabrication process of DSSVs interposer is introduced, and the superiority of the double-sided interconnection process with two etch-stop layers is described in detail. The impact of different T-vias depth on DSSVs interconnections in the same wafer is discussed and two times PI opening processes are proposed to eliminate air bubbles in the B-via. The relationship between the interposer thickness and warpage is studied by finite element analysis simulation and experiment. The prototype of the DSSVs interposer with a size of 100  × 100 mm and a thickness of 318.2 µm is fabricated, and electrical tests including short tests and continuity tests are carried out.

This paper proposes a large-sized and stand-alone interposer based on DSSVs interconnection.

Concerning the radiation effects on the three-dimensional (3D) packaging in space environment, this study aims to investigate the influence of the total dose effect on the transmission characteristics of high-frequency electrical signals using experimental and simulation methods.

This work carries out the irradiation test of the specimens and measures their S21 parameters before and after irradiation. A simulation model describing the total dose effect was built based on the experimental test results. And, the radiation hardening design is evaluated by the simulation method.

The experimental results demonstrate that the S21 curve of the interconnection decreases with the increase of the irradiation dose, indicating that the total dose effect leads to the decline of its signal transmission characteristics. According to the simulation results, decreasing the height of the through silicon via (TSV), increasing the radius of the TSV, reducing the length of Si and increasing the number of grounded through silicon via have positive effects on improving the radiation resistance of the interconnection structure.

This work investigates the effect of radiation on the transmission characteristics of interconnection structures for 3D packaging and proposes the hardening design methods. It is meaningful for improving the reliability of 3D packaging in space applications.

By investigating the thermal-mechanical interaction between the through silicon via (TSV) and the Cu pad, this study aimed to determine the effect of electroplating defects on the upper surface protrusion and internal stress distribution of the TSV at various temperatures and to provide guidelines for the positioning of TSVs and the optimization of the electroplating process.

A simplified model that consisted of a TSV (100 µm in diameter and 300 µm in height), a covering Cu pad (2 µm thick) and an internal drop-like electroplating defect (which had various dimensions and locations) was developed. The surface overall deformation and stress distribution of these models under various thermal conditions were analyzed and compared.

The Cu pad could barely suppress the upper surface protrusion of the TSV if the temperature was below 250 ?. Interfacial delamination started at the collar of the TSV at about 250 ? and became increasingly pronounced at higher temperatures. The electroplating defect constantly experienced the highest level of strain and stress during the temperature increase, despite its geometry or location. But as its radius expanded or its distance to the upper surface increased, the overall deformation of the upper surface and the stress concentration at the collar of the TSV showed a downward trend.

Previous studies have not examined the influence of the electroplating void on the thermal behavior of the TSV. However, with the proposed methodology, the strain and stress distribution of the TSV under different conditions in terms of temperature, dimension and location of the electroplating void were thoroughly investigated, which might be beneficial to the positioning of TSVs and the optimization of the electroplating process.

The substrate coupling and loss in integrated circuits are analyzed. Then, the authors extract impedances between any numbers of embedded contacts. The paper aims to discuss these issues.

The paper proposes a new substrate network 3D extraction technique, adapted from a transmission line method or Green kernels, but in the whole volume.

Extracting impedances between any numbers of embedded contacts with variable shapes or/and through silicon via. This 3D method is much faster comparing with FEM

Previous works consider TSVs alone, contacts onto the substrate. The authors do study entanglement between the substrate and the interconnections.

This paper aims to develop the thermal resistance network model based on the heat dissipation paths from the multi-die stack to the ambient and takes into account the composite effects of the thermal spreading resistance and one-dimensional (1D) thermal resistance. The thermal spreading resistance comprises majority of the thermal resistance when heat flows in the horizontal direction of a large plate. The present study investigates the role of determining the temperature increase compared to the thermal resistances intrinsic to the 3D technology, including the thermal resistances of bonding layers and through silicon vias (TSVs).

This paper presents an effective method that can be applied to predict the thermal failure of the heat source of silicon chips. An analytical model of the 3D integrated circuit (IC) package, including the full structure, is developed to estimate the temperature of stacked chips. Two fundamental theories are used in this paper – Laplace’s equation and the thermal resistance network – to calculate 1D thermal resistance and thermal spreading resistance on the 3D IC package.

This paper provides a comprehensive model of the 3D IC package, thus improving the existing analytical approach for predicting the temperature of the heat source on the chip for the 3D IC package.

Based on the aforementioned shortcomings, the present study aims to determine if the use of an analytical resistance model would improve the handling of a temperature increase on the silicon chips in a 3D IC package. To achieve this aim, a simple rectangular plate is utilized to analyze the temperature of the heat source when applying the heat flux on the area of the heat source. Next, the analytical model of a pure plate is applied to the 3D IC package, and the temperature increase is analyzed and discussed.

The main contribution of this paper is the use of a simple concept and a theoretical resistance network model to improve the current understanding of thermal failure by redesigning the parameters or materials of a printed circuit board.

In this paper, an analytical model of a 3D IC package was proposed based on the calculation of the thermal resistance and the analysis of the network model.

The aim of this work was to estimate the mean temperature of the silicon chips and understand the heat convection paths in the 3D IC package. The results reveal these phenomena of the complete structure, including TSV and bump, and highlight the different thermal conductivities of the materials used in creating the 3D IC packages.

The purpose of this study is to numerically assess the misalignment-induced deformation and its implications, in the through-silicon via (TSV), silicon chip, solder micro-bump, and bonding layer.

The 3D finite element model features a TSV/micro-bump bonding structure connecting two adjacent silicon (Si) chips, with and without an underfill layer between. A case that the entire solder layer has transformed into an intermetallic layer is also considered.

The existence of an underfill layer enhances the overall resistance to shear deformation, although with a higher buildup of local stresses. High shear and tensile stresses can develop in the intermetallic and nearby regions of copper and Si if the solder alloy is replaced by an intermetallic layer. The carrier mobility change in Si may be extensively affected by the mechanical action, even in regions far away from the TSV.

This work parametrically explores the trend of stress and deformation fields due to mechanical shear and its influences on the electrical performance of devices. Potential for damage initiation in the TSV/micro-bump is also examined.

A W-band antennas-in-packages (AIP) module with a hybrid stacked glass-compound wafer level fan-out process was presented. Heterogeneous radio frequency (RF) chips were integrated into one single module with a microscale fan-out process. This paper aims to find a new strategy for 5G communication with 3D integration of multi-function chips.

The AIP module was composed of two stacked layers: the antenna layer and RF layer. After architecture design and performance simulation, the module was fabricated, The 8 × 8 antenna array was lithography patterned on the 12 inch glass wafer to reduce the parasitic parameters effect, and the signal feeding interface was fabricated on the backside of the glass substrate.

AIP module demonstrates a size of 180 mm × 180mm × 1mm, and its function covers the complete RF front-end chain from the antenna to signal to process and can be applied in 5 G communication and automotive components.

With three RF multi-function chips and two through silicon via (TSV) chips were embedded in the 12 inch compound wafer through the fan-out packaging process; two layers were interconnected with TSV and re-distributed layers.

The purpose of this paper is to demonstrate a novel 3D system-in-package (SiP) approach. This new packaging approach is based on stacked silicon submount technology. As demonstrators, a smart lighting module and a sensor systems were successfully developed by using the fabrication and assembly process described in this paper.

The stacked module consists of multiple layers of silicon submounts which can be designed and fabricated in parallel. The 3D stacking design offers higher silicon efficiency and miniaturized package form factor. This platform consists of silicon submount design and fabrication, module packaging, system assembling and testing and analyzing.

In this paper, a smart light emitting diode system and sensor system will be described based on stacked silicon submount and 3D SiP technology. The integrated smart lighting module meets the optical requirements of general lighting applications. The developed SiP design is also implemented into the miniaturization of particular matter sensors and gas sensor detection system.

SiP has great potential of integrating multiple components into a single compact package, which has potential implementation in intelligent applications.