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The purpose of this paper is to demonstrate a simple fiber sensor for simultaneous measurement of liquid refractive-index (RI) and temperature.

The sensor structure is formed by a long period fiber grating cascaded with a section of thin-core fiber. The long period fiber grating is fabricated on single mode fiber, followed by a section of 20-mm length thin-core fiber which is a modal interferometer.

Cladding mode interference between long period fiber grating and thin-core fiber modal interferometer is weak in the experimental investigation. Both of these two cladding mode type fiber devices are sensitive to surrounding RI and temperature. So the RI and temperature can be measured simultaneously by monitoring the spectral characteristics of the compound sensor. The sensitivity is calibrated and sensor matrix is provided in the experiment.

This proposed fiber sensor is simple, tough, cost-effective and suitable for discriminate the liquid RI and temperature with high sensitivity.

Peel strength numbers are part of a laminate's specifications and should characterize the specific bond performance (copper adhesion) under test conditions. Unfortunately, from both a theoretical and a practical point of view they are not able to do that. This study seeks to address this issue.

This paper has been written to show the main impacts on the measured peel strength numbers in the IPC‐TM‐650 peeling test. From an extensive database regarding peel numbers for diverse foil types, foil thicknesses and treatment roughnesses it is possible to show the influence of prepreg type, foil thickness and roughness on the measure peel strength.

Copper adhesion to laminating resin is insufficiently described by peel strength data because of the impacts of foil thickness, stiffness on bending (physical bending work, stress distribution underneath the peeling line) and the treatment roughness. The latter works reinforcing regarding the (low) resin strength and this influence is measured on resin strength instead of real bond. Fracture due to peeling is cohesive, mostly with a totally intact copper‐resin interface. This is especially true in high performance laminates that show low peel strengths not because of bad copper bonding but because of brittle resins (filled and unfilled).

Users have to understand the limited benefit of the IPC peel test in characterizing copper‐resin bonds. Peel increase on (low bond) high performance resins by increased foil roughness is not a practical way in the field because of no bond improvement (interface) and heavy disadvantages in dielectric thickness (HiPot tests at thin core laminates), respectively.

THIS paper describes work done to translate the theory of Structural Sandwich Panel Design into a form in which it could be used for rapid estimation in a design office.

The driving forces behind recent significant improvements in organic packages for microelectronic applications are electrical performance, product weight, size and manufacturing cost. A very careful selection of optimum manufacturing processes, equipment and materials, and stringent control of critical manufacturing operations are prerequisites for success in this emerging market place. Major technical and business related challenges to a printed circuit board manufacturer who plans to enter this market are discussed.

Describes preliminary structural design work on a notional uninhabited tactical aircraft (UTA), carried out at Cranfield University. UTAs are seen as an important future element of military fleets. A notional baseline requirement was derived, leading to the evolution of a design solution. The basic requirements for such a UTA are naturally highly classified but, although industry has been hesitant to comment, the baseline requirements and design solution developed herein are believed to be reasonable.

Embedded passives account for a very large part of today's electronic assemblies. This is particularly true for products such as cellular phones, camcorders, computers, and several critical defence devices. Market pressures for new products with more features, smaller size and lower cost demand smaller, compacter, simpler substrates. An obvious strategy is to reduce the number of surface mounted passives by embedding them in the substrate. In addition, current interconnect technology to accommodate surface mounted passives imposes certain limits on board design which constrain the overall system speed. Embedding passives is one way to minimize the functional footprint while at the same time improving performance. The purpose of this paper is to describe the development of a thin film technology based on ferroelectric‐epoxy polymer‐based flake‐free resin coated copper capacitive (RC3) nanocomposites to manufacture multilayer embedded capacitors.

This paper discusses thin film technology based on RC3 nanocomposites. In particular, recent developments in high capacitance, large area, thin film passives, and their integration in system in a package (SiP) are highlighted.

A variety of RC3 nanocomposite thin films ranging from 8 to 50 microns thick were processed on copper substrates by liquid coating. Multilayer embedded capacitors resulted in high capacitances of 16‐28 nF. The fabricated test vehicle also included two embedded resistor layers with resistances in the range of 15 Ω to 100 kΩ. To enable high performance devices, an embedded resistor must meet certain tolerances. The embedded resistors can be laser trimmed to a tolerance of <5 percent, which is usually acceptable for most applications. An extended embedded passives solution has been demonstrated, both through its high wireability designs and package performance, to be perfectly suited for SiP applications.

This case study designed and fabricated an eight layer high density internal passive core and subsequently applied fine geometry three buildup layers to form a 3‐8‐3 structure. The passive core technology is capable of providing up to six layers of embedded capacitance and could be extended further.

A thin film technology based on ferroelectric‐epoxy polymer‐based flake‐free RC3 nanocomposites was developed to manufacture multilayer embedded capacitors. The overall approach lends itself to package miniaturization because capacitance can be increased through multiple layers and reduced thickness to give the desired values in a smaller area.

Emerging ‘chip‐size’ packages, and bare flip‐chips, require new substrate properties if high lead count chips are to be reliably interconnected on printed wiring boards and multichip modules at low cost. Blind via holes have been shown to increase interconnect density significantly without adding layers which contribute to high cost. Until recently, the use of blind vias has been limited to high‐end applications since standard fabrication methods, either sequential lamination or controlled depth drilling, are too slow and expensive for most high volume commercial applications. To maintain a low layer count while interconnecting higher I/O packages, commercial and consumer electronics require a substrate technology which supports high speed, micro‐via hole formation. This paper describes a process for fabricating high speed micro‐vias in dimensionally stable non‐woven Aramid reinforced laminates using laser ablation technology. Laser equipment capable of producing over 100 blind micro‐via holes per second is discussed. The process steps of hole cleaning and plating are reviewed, showing how existing PWB manufacturing technologies can be used. This process is compared with other methods of generating small holes and blind vias in printed wiring boards. In addition, requirements for flip‐chip and chip‐size packages, including a coefficient of thermal expansion of <10 ppm/°C and thin laminate dimensional stability of <0.03%, are explained.

Although vacuum insulation panels (VIPs) are thermal insulators that combine high thermal performance with limited thickness, application in the building sector is still rare due to lack of scientific knowledge on the behaviour of these panels applied in building constructions. This paper, therefore, seeks to give an overview of the requirements for and the behaviour of VIPs integrated into building components and constructions. Moreover, the interaction between different requirements on and properties of these integrated components are discussed in detail, since a desired high quality of the finished product demands an integral approach regarding all properties and requirements, especially during the design phase. Therefore, the importance of an integral design approach to application of VIPs is shown and emphasized in this paper.

To achieve this objective, the legally and technically required properties of VIPs and especially their interrelationships have been studied, resulting in a relationship diagram. Based on these investigations of thermal‐ , service life‐ and structural‐properties have been selected to be studied more elaborately using experimental set‐up for structural testing and simulation software for thermal and hygrothermal testing.

Two relationships between requirements or properties were found to be of principal importance for the design of façade components in which VIPs are integrated. First, thermal performance requirements strongly interact with structural performance, principally through the edge spacer of this façade component. A high thermal performance requires minimization of the thermal edge effect, in most cases reducing the structural performance of the entire panel. Second, an important relationship between thermal performance and service life has been recognised. The operating phenomenon mainly governing this interaction is thermal conductivity aging.

Most research in the field of vacuum insulation until now has been directed towards gaining knowledge on specific properties of the product, especially on thermal and hygrothermal properties. The relationships and interactions between these properties and the structural behaviour, however, have been neglected. This paper, therefore, addresses the need for an integral design (and study) approach for the application of VIPs in architectural constructions.

This paper looks at the implications of increases in system speed and density for the interconnection system, noting particularly the increased requirements placed on the substrate and tracking system. It reviews the properties required of substrates and the limitations derived from the materials used and the processes needed to put tracks on them. Those areas where these requirements are in conflict are highlighted, including such low technology problems as the limited size availability of substrate prepregs which may limit the tracking density achievable on the newer, more advanced low dielectric materials. Some limitations and trade‐offs are identified.