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This paper aims to review comprehensively the different voltage-boosting techniques and classifies according to their voltage gain, stress on the semiconductor devices, count of the total components and their prominent features. Hence, the focus is on non-isolated step-up converters. The converters categorized are analyzed according to their category with graphical representation.

Many converters have been reported in recent years in the literature to meet our power requirements from mill watts to megawatts. Fast growth in the generation of renewable energy in the past few years has promoted the selection of suitable converters that directly impact the behaviour of renewable energy systems. Step-up converters are a fast-emerging switching power converter in various power supply units. Researchers are more attracted to the derivation of novel topology with a high voltage gain, low voltage and current stress, high efficiency, low cost, etc.

A comparative study is done on critical metrics such as voltage gain, switch voltage stress and component count. Besides, the converters are also summarized based on their advantages and disadvantages. Furthermore, the areas that need to be explored in this field are identified and presented.

Types of analysis usually performed in dc converter and their needs with the areas need to be focused are not yet completely reviewed in most of the articles. This paper gives an eyesight on these topics. This paper will guide the researchers to derive and suggest a suitable topology for the chosen application. Moreover, it can be used as a handbook for studying the various topologies with their shortfalls, which will provide a way for researchers to focus.

In parallel sampling method, the size of the sampling capacitor is reduced to improve the bandwidth of the ADC.

Various low-power techniques for 10-bit 200MS/s pipelined analog-to-digital converter (ADC) are presented. This work comprises two techniques including parallel sampling and switched op-amp sharing technique.

This paper aims to study the effect of parallel sampling and switched op-amp sharing techniques on power consumption in pipelined ADC. In switched op-amp sharing technique, the numbers of op-amps used in the stages are reduced. Because of the reduction in the size of capacitors in parallel sampling technique and op-amps in the switched op-amp sharing technique, the power consumption of the proposed pipelined ADC is reduced to a greater extent.

Simulated the 10-bit 200MS/s pipelined ADC with complementary metal oxide semiconductor process and the simulation results shows a maximum differential non-linearity of +0.31/−0.31 LSB and the maximum integral non-linearity (of +0.74/−0.74 LSB with 62.9 dB SFDR, 55.90 dB SNDR and ENOB of 8.99 bits, respectively, for 18mW power consumption with the supply voltage of 1.8 V.

This paper aims to propose a new unified and non-ideal switch model for analysis of switching circuits.

The model has a single unified structure that includes all possible states (on, off) of the switches. The analysis with the proposed switch model requires only one topology and uses the single system equation regardless of states of switches. Moreover, to improve accuracy, the model contains the on-state resistance and capacitive effect of switches. The system equations and the states of switches are updated by control variables, used in the model.

There are no restrictions on circuit topology and switch connections. Switches can be internally and externally controlled. The non-ideal nature of the model allows the switch to be modeled more realistically and eliminates the drawbacks of the ideal switch concept. After modeling with the proposed switch model, a linear circuit is obtained. Two examples related to switching circuits are included into the study. The results confirm the accuracy of the model.

This paper contributes a different switch model for analysis of switching converters to the literature. The main advantage of the model is that it has a unified and non-ideal property. With the proposed switch model, the transient events, like voltage spikes and high-frequency noises, caused by inductor and capacitor elements at switching instants can be observed properly.

The paper aims to emphasise how switched systems can be analysed with elementary techniques which require only undergraduate-level linear algebra and differential equations. It is also emphasised how math software can become useful for simplifying analytic complications.

The time domain voltage balance methodology is used for stability analysis. As for deriving formulas for the asymptotic average of both capacitor voltage and inductor current, a new simple analytic method is introduced.

It was shown analytically that the time average of capacitor voltage converges to half of the source voltage. A formula for the time average of the current of the inductor is also computed. As a by-product, it was discovered that the period of the current is half of the switching period. Numerical simulations are obtained to illustrate the accuracy of the results.

Higher dimensional generalisations could become a bit complicated, as stability analysis of higher dimensional exponential matrices is not so easy to handle. On the other hand, the new discovery on the period of the current is more likely to give new insights into handling higher dimensional systems.

Analytical formulas are exact, and it helps in accurately modelling flying capacitor converts (FCCs) in practice.

FCC is well studied in engineering society. However, not much is done in obtaining closed form solutions using analysis. Also, math software is much used in computation of numerical results and obtaining simulations. In this paper, one more important aspect of math software is emphasised, namely, use symbolic and numeric computing environment Maple in analysis.

The purpose of this paper is to present analysis of the feedback predictive encoder-based analog-to-digital converter (ADC).

The use of feedback predictive encoder-based ADCs presents an alternative to the traditional two-stage pipeline ADC by replacing the input estimate producing first stage of the pipeline with a predictive loop that also produces an estimate of the input signal.

The overload condition for feedback predictive encoder ADCs is dependent on input signal amplitude and frequency, system gain and filter order. The limitation on the practical usable filter order is set by limit cycle oscillation. A boundary condition is defined for determination of maximum usable filter order. In a practical implementation of the predictive encoder ADC, the time allocated to the key functions of the gain stage and loop quantizer leads to optimization of the power consumption.

A practical switched capacitor implementation of the predictive encoder-based ADC is proposed. The power consumption of key circuit blocks is investigated.

This paper presents a methodology to optimize the bandwidth of predictive encoder ADCs. The overload and stability conditions may be used to determine the maximum input signal bandwidth for a given loop quantizer. Optimization of power consumption based on the allocation of time between the gain stage and the successive approximation register ADC operation is investigated. The lower bound of power consumption for this architecture is estimated.

Control-signal-to-output-voltage transfer function of the conventional boost converter has at least one right-half plane zero (RHPZ) in the continuous conduction mode which can restrict the open-loop bandwidth of the converter. This problem can complicate the control design for the load voltage regulation and conversely, impact on the stability of the closed-loop system. To remove this positive zero and improve the dynamic performance, this paper aims to suggest a novel boost topology with a step-up voltage gain by developing the circuit diagram of a conventional boost converter.

Using a transformer, two different pathways are provided for a classical boost circuit. Hence, the effect of the RHPZ can be easily canceled and the voltage gain can be enhanced which provides conditions for achieving a smaller working duty cycle and reducing the voltage stress of the power switch. Using this technique makes it possible to achieve a good dynamic response compared to the classical boost converter.

The observations show that the phase margin of the proposed boost converter can be adequately improved, its bandwidth is largely increased, due to its minimum-phase structure through RHPZ cancellation. It is suitable for fast dynamic response applications such as micro-inverters and fuel cells.

The introduced method is analytically studied via determining the state-space model and necessary criteria are obtained to achieve a minimum-phase structure. Practical observations of a constructed prototype for the voltage conversion from 24 V to 100 V and various load conditions are shown.

This paper aims to better design the resonant tank parameters for LLC resonant converter. And, it is found that under heavy load, the voltage gain is affected by junction capacitors of the primary side switching and the parasitic parameters of the secondary side diodes converted to the primary side, which will cause the voltage gain decreased when the switching frequency decreased.

This paper proposes an optimization parameters design method to solve this problem, which was based on impedance model considering the parasitic parameters of switching devices and diodes.

The effectiveness of the proposed method is verified by impedance Bode plots and experimental results.

From the perspective of impedance modeling, this paper finds the reasons for the insufficient voltage regulation capability of LLC resonant converters under heavy load and finds solutions through analysis.

The purpose of this paper is to present the Switched Inductor Z-Source Inverter (SLZSI) topology for three-phase on-line uninterruptible power supply (UPS) by employing third harmonic injected maximum constant boost pulse width modulation (PWM) control. Conventional UPS consists of step-up transformer or boost chopper along with voltage source inverter (VSI) which reduces the efficiency and increases energy conversion cost. The proposed three-phase UPS by using SLZSI has the voltage boost capability through shoot through zero state which is not available in traditional VSI and current source inverter.

Performance of three-phase on-line UPS based on ZLZSI by using third harmonic injected maximum constant boost PWM control is analyzed and evaluated in MATLAB/Simulink software and the results are compared with Z-source inverter (ZSI) fed UPS. Experimental results are presented for the validation of the simulation and theoretical analysis.

The output voltages, currents, THD values, voltage stress and efficiencies for different loading condition are determined and compared with the theoretical values and UPS with ZSI. The experimental results validate the theoretical and simulation results.

Compared with the traditional ZSI, the SLZSI provides high-voltage boost inversion ability with a very short shoot through zero state. This proposed UPS by using SLZSI increases the efficiency with less number of components, reduces the harmonics, increases the voltage gain and reduces the voltage stress.

Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC.

A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration.

The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms.

The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

Growing concerns about the depletion of fossil fuels and global awareness about the environmental pollution motivate the automobile industries to search for an alternative transportation system such as hybrid vehicular systems, plug-in hybrid vehicular systems and electric vehicular systems. To have carbon emission-free environment, these electric vehicles use renewable sources, such as solar and fuel cell, as primary source of supply. As these renewable sources are intermittent in nature, an energy buffer such as battery or super capacitor is required for the smooth supply and regulation of load power. The current electric vehicle systems use multistage power electronic converters for energy transfer. Therefore, this paper aims to propose a modified multiport converter based on Luo topology.

The suggested converter is developed based on Luo topology using voltage lift technique.

Most of the research presents buck boost converter as power electronic interface in electric vehicle applications. Whereas the converter proposed in this paper is based on Luo topology. It exhibits the features of single stage conversion between the input output ports, with less ripple, high efficiency, fewer components and centralized control for effective power management.

The presented converter can work in all possible modes such as buck and boost modes independently or simultaneously during various operating conditions of electric vehicles. During buck/boost mode, the primary source PV (Photovoltaic) in the converter provides the required power for the vehicle and charges the secondary source, i.e. battery, whereas during boost mode the battery supplies the sufficient power to load.