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This paper aims to investigate the effect of physical vapor deposition (PVD)-coated stencil wall aperture on the life span of fine-pitch stencil printing.

The fine-pitch stencil used in this work is fabricated by electroform process and subsequently nano-coated using the PVD process. Stencil printing process was then performed to print the solder paste onto the printed circuit board (PCB) pad. The solder paste release was observed by solder paste inspection (SPI) and analyzed qualitatively and quantitatively. The printing cycle of up to 80,000 cycles was used to investigate the life span of stencil printing.

The finding shows that the performance of stencil printing in terms of solder printing quality is highly dependent on the surface roughness of the stencil aperture. PVD-coated stencil aperture can prolong the life span of stencil printing with an acceptable performance rate of about 60%.

Stencil printing is one of the important processes in surface mount technology to apply solder paste on the PCB. The stencil’s life span greatly depends on the type of solder paste, stencil printing cycles involved and stencil conditions such as the shape of the aperture, size and thickness of the stencil. This study will provide valuable insight into the relationship between the coated stencil wall aperture via PVD process on the life span of fine-pitch stencil printing.

In the electronic assembly industry, low-temperature soldering holds great potential to be used in surface mounting technology. Tin–bismuth (Sn–Bi) eutectic alloys are lead-free solders applied in consumer electronics because of their low melting point, high strength and low cost. This paper aims to investigate how to address the problem of hot tear crack formation during Sn–Bi low-temperature solder (LTS) in the mass production of consumer electronics.

This paper explored the development of hot tear cracks during Sn–Bi soldering in the fabrication of flip chip ball grid arrays. Experiments were designed to simulate various conditions encountered in Sn–Bi soldering. Quantitative analysis was conducted on the number of hot tear cracks observed in different alloy compositions and solder volumes to explore the primary cause of hot tear cracks and possible methods to suppress crack formation.

Hot tear cracks existed in Sn–Bi solders with different bismuth (Bi) contents, but increasing the solder volume reduced the number of hot tear cracks. Experiments were designed to test the degree of chip transient thermal warpage with temperature change, and, according to the results, glue was dispensed in specific areas to reduce chip warpage deformation. Finally, the results of combined process experiments pointed to an effective method of low-temperature soldering to suppress hot tear cracks.

The study focuses on Sn–Bi solders only without other solder pastes such as SAC305 or Sn–Zn series.

With the growing popularity of smart electronics, especially in intelligent terminals, new energy vehicles electronics, solar photovoltaic and other field, there will be more and more demand for low- temperature, energy-saving, lead-free solders. Therefore, this study will help the industry to roll out LTS (Sn–Bi) solutions rapidly.

In the long term, lean and green manufacturing is expected to be essential for maintaining an advanced manufacturing industry across the world. Developing new LTSs and soldering processes is the most effective, direct solution for energy conservation and emission mitigation. With the growing popularity of smart electronics, especially in intelligent terminals, new energy vehicles and solar photovoltaics, there would be an increased demand for low-temperature, energy-saving, lead-free techniques.

Although there are many methods that can be used to suppress hot tear cracks, there is little research on how to control the hot tear cracks caused by the low-temperature soldering of Sn–Bi in laptop applications. The authors studied the hot tear cracks that developed during the world’s first mass production of 50 million personal laptops based on low-temperature Sn–Bi alloy solder pastes. By controlling the Bi content, redesigning the solder paste printing process (e.g. through a printer’s stencil) and adding dispensing processes, the authors obtained reliable and stable experimental data and conclusions.

This study aims to focus on the surface mount technology (SMT) mass production process of Sn-9Zn-2.5Bi-1.5In solder. It explores it with some components that will provide theoretical support for the industrial SMT application of Sn-Zn solder.

This study evaluates the properties of solder pastes and selects a more appropriate reflow parameter by comparing the microstructure of solder joints with different reflow soldering profile parameters. The aim is to provide an economical and reliable process for SMT production in the industry.

Solder paste wettability and solder ball testing in a nitrogen environment with an oxygen content of 3,000 ppm meet the requirements of industrial production. The printing performance of the solder paste is good and can achieve a printing rate of 100–160 mm/s. When soldering with a traditional stepped reflow soldering profile, air bubbles are generated on the surface of the solder joint, and there are many voids and defects in the solder joint. A linear reflow soldering profile reduces the residence time below the melting point of the solder paste (approximately 110 s). This reduces the time the zinc is oxidized, reducing solder joint defects. The joint strength of tin-zinc joints soldered with the optimized reflow parameters is close to that of Sn-58Bi and SAC305, with high joint strength.

This study attempts to industrialize the application of Sn-Zn solder and solves the problem that Sn-Zn solder paste is prone to be oxidized in the application and obtains the SMT process parameters suitable for Sn-9Zn-2.5Bi-1.5In solder.

This study aims to investigate the possible defects and their root causes in a soft-termination multilayered ceramic capacitor (MLCC) when subjected to a thermal reflow process.

Specimens of the capacitor assembly were subjected to JEDEC level 1 preconditioning (85 °C/85%RH/168 h) with 5× reflow at 270°C peak temperature. Then, they were inspected using a 2 µm scanning electron microscope to investigate the evidence of defects. The reliability test was also numerically simulated and analyzed using the extended finite element method implemented in ABAQUS.

Excellent agreements were observed between the SEM inspections and the simulation results. The findings showed evidence of discontinuities along the Cu and the Cu-epoxy layers and interfacial delamination crack at the Cu/Cu-epoxy interface. The possible root causes are thermal mismatch between the Cu and Cu-epoxy layers, moisture contamination and weak Cu/Cu-epoxy interface. The maximum crack length observed in the experimentally reflowed capacitor was measured as 75 µm, a 2.59% difference compared to the numerical prediction of 77.2 µm.

This work's contribution is expected to reduce the additional manufacturing cost and lead time in investigating reliability issues in MLCCs.

Despite the significant number of works on the reliability assessment of surface mount capacitors, work on crack growth in soft-termination MLCC is limited. Also, the combined experimental and numerical investigation of reflow-induced reliability issues in soft-termination MLCC is limited. These cited gaps are the novelties of this study.

This paper aims to investigate the effect and mechanism of O atom single doping, Ce and O atoms co-doping on the interfacial microscopic behavior of brazed Ni-Cr/diamond.

Using first-principles calculations, the embedding energy, work of separation, interfacial energy and electronic structures of Ni-Cr-O/diamond and Ni-Cr-O-Ce/diamond interface models were calculated. Then, the effect of Ce and O co-doping was experimentally verified through brazed diamond with CeO₂-added Ni-Cr filler alloy.

The results show that O single-doping reduces the interfacial bonding strength between Ni-Cr filler alloy and diamond but enhances its interfacial stability to some extent. However, the Ce and O co-doping simultaneously enhances the interfacial bonding strength and stability between Ni-Cr filler alloy and diamond. The in-situ formed Ce-O oxide at interface impedes the direct contact between diamond and Ni-Cr filler alloy, which weakens the catalytic effect of Ni element on diamond graphitization. It is experimentally found that the fine rod-shaped Cr₃C₂ and Cr₇C₃ carbides are generated on diamond surface brazed with CeO₂-added Ni-Cr filler alloy. After grinding, the brazed diamond grits, brazed with CeO₂-added Ni-Cr filler alloy, present few fracture and the percentage of intact diamond reaches 67.8%. Compared to pure Ni-Cr filler alloy, the brazed diamond with CeO₂-added Ni-Cr filler alloy exhibit the better wear resistance and the slighter thermal damage.

Using first-principles calculations, the effect of Ce and O atoms co-doping on the brazed diamond with Ni-Cr filler alloy is investigated, and the calculation results are verified experimentally. Through the first-principles calculations, the interface behavior and reaction mechanism between diamond and filler alloy can be well disclosed, and the composition of filler alloy can be optimized, which will be beneficial for synergistically realizing the enhanced interface bonding and reduced thermal damage of brazed diamond.

Statistical modeling has been successfully applied to integrated circuit (IC) solder joint inspection. However, there are some inherent problems in previous statistical modeling methods. This paper aims to propose an adaptive statistical modeling method to further improve the inspection performance for IC solder joints.

First, different pixels in the IC solder joint image were modeled by different templates, each of which was composed of the hue value of the pixel and a proposed template significance factor. Then, the potential defect image was obtained by adaptive template matching and the potential defect threshold for each pixel. It was noted that the number of templates, matching distance threshold, potential defect threshold and updating rate were adaptively updated during model training. Finally, the trained statistical model was used to inspect the IC solder joints by means of defect degree.

Experimental results indicated that the proposed adaptive schemes greatly contributed to the inspection performance of statistical modeling. Also, the proposed inspection method achieved better performance compared with some state-of-the-art inspection methods.

The proposed method offers a promising approach for IC solder joint inspection, which establishes different numbers of templates constructed by pixel values and template significance factors for different pixels. Also, some important parameters were adaptively updated with the updating of the model, which contributed to the inspection performance of the model.

The purpose of this paper is to illustrate the new technical demands and reliability challenges to printed circuit board (PCB) designs, materials and processes when the transmission frequency increases from Sub-6 GHz in previous generations to millimeter (mm) wave in fifth-generation (5G) communication technology.

The approach involves theoretical analysis and actual case study by various characterization techniques, such as a stereo microscope, metallographic microscope, scanning electron microscope, energy dispersive spectroscopy, focused ion beam, high-frequency structure simulator, stripline resonator and mechanical test.

To meet PCB signal integrity demands in mm-wave frequency bands, the improving proposals on copper profile, resin system, reinforcement fabric, filler, electromagnetic interference-reducing design, transmission line as well as via layout, surface treatment, drilling, desmear, laminating and electroplating were discussed. And the failure causes and effects of typical reliability issues, including complex permittivity fluctuation at different frequencies or environments, weakening of peel strength, conductive anodic filament, crack on microvias, the effect of solder joint void on signal transmission performance and soldering anomalies at ball grid array location on high-speed PCBs, were demonstrated.

The PCB reliability problem is the leading factor to cause failures of PCB assemblies concluded from statistical results on the failure cases sent to our laboratory. The PCB reliability level is very essential to guarantee the reliability of the entire equipment. In this paper, the summarized technical demands and reliability issues that are rarely reported in existing articles were discussed systematically with new perspectives, which will be very critical to identify potential reliability risks for PCB in 5G mm-wave applications and implement targeted improvements.

This study aims to review the effect of copper percentage in Sn-based solder alloys (Sn-xCu, x = 0–5 Wt.%) on intermetallic compound (IMC) formation and growth after laser soldering.

This study reviews the interfacial reactions at the solder joint interface, solder joint morphology and the theory on characterizing the formation and growth of IMCs. In addition, the effects of alloying and strengthening mechanism, including wettability, melting and mechanical properties are discussed.

This paper presents a comprehensive overview of the composition of tin-copper (Sn-Cu) solders with a potential to enhance their microstructure, mechanical characteristics and wettability by varying the Cu percentage. The study found that the best Cu content in the Sn-xCu solder alloy was 0.6–0.7 Wt.%; this composition provided high shear strength, vibration fracture life value and ideal IMC thickness. A method of solder alloy preparation was also found through powder metallurgy and laser soldering to improve the solder joint reliability.

This study focuses on interfacial reactions at the solder joint interface, solder joint morphology, modelling simulation of joint strength and the theory on characterising the formation and growth of IMC.

The paper comprehensively summarises the useful findings of the Sn-Cu series. This information will be important for future trends in laser soldering on solder joint formation.

Pb-free solders have been developed to replace the standard Sn–Pb eutectic solder since the prohibition on Pb used in solders. The Sn–Ag–Cu series of lead-free solders is the most extensively used in the electronics industry. The Ag₃Sn, which forms during isothermal ageing, can significantly degrade solder joint reliability. Sn–Ag–Cu solder’s high price further hindered its use in the electronics industry. This paper aims to investigate different copper percentages into Sn–xCu solder alloy to improve its microstructure and strength performance.

The solder alloys used in this work were Sn–xCu, where x = 0.0, 0.3, 0.5, 0.7, 1.0 Wt.%, which was soldered onto electroless nickel immersion gold (ENIG) substrate using carbon dioxide (CO₂) gas laser. Then these samples were subjected to isothermal aging for 0, 200, 500, 1,000 and 2,000 h. The Sn–xCu solder alloy was fabricated through a powder metallurgy process.

Microstructure characterization showed that Cu addition resulted in fine and rounded shape of Cu–Sn–Ni particles. Shear strength of Sn–xCu solder joints was increased with increasing Cu content, but at aging duration of 1,000 h, it dropped slightly. It is believed that the strength improved due to the increment of diffusion rate during isothermal aging.

In a Cu–Sn solder, the recommended amount is 1.0 Wt.% of Cu. In extensive aging procedures, it was discovered that Sn1.0Cu solder improved the reliability of solder joints. The findings indicated that the innovative solder alloys might satisfy the needs of high-reliability applications.

The study shows that the right amount of Cu enhances the solidification of Sn–Cu solder, increasing the shear force of the Cu–Sn solder joint. The Sn1.0Cu exhibits a ductile fracture on the top microstructure, improving the joint’s average shear strength.

The purpose of this study is to propose a simplifying approach for modelling a reliability test. Modelling the reliability tests of printed circuit board (PCB)/microelectronic component assemblies requires the adoption of several simplifying assumptions. This study introduces and validates simplified assumptions for modeling a four-point bend test on a PCB/wafer-level chip scale packaging assembly.

In this study, simplifying assumptions were used. These involved substituting dynamic imposed displacement loading with an equivalent static loading, replacing the spherical shape of the interconnections with simplified shapes (cylindrical and cubic) and transitioning from a three-dimensional modelling approach to an equivalent two-dimensional model. The validity of these simplifications was confirmed through both quantitative and qualitative comparisons of the numerical results obtained. The maximum principal plastic strain in the solder balls and copper pads served as the criteria for comparison.

The simplified hypotheses were validated through quantitative and qualitative comparisons of the results from various models. Consequently, it was determined that the replacement of dynamic loading with equivalent static loading had no significant impact on the results. Similarly, substituting the spherical shape of interconnections with an equivalent shape and transitioning from a three-dimensional approach to a two-dimensional one did not substantially affect the precision of the obtained results.

This study serves as a valuable resource for researchers seeking to model accelerated reliability tests, particularly in the context of four-point bending tests. The results obtained in this study will assist other researchers in streamlining their numerical models, thereby reducing calculation costs through the utilization of the simplified hypotheses introduced and validated herein.