Search results

Implementing surface mount technology (SMT) into military systems has not progressed as rapidly as expected. One of the major reasons is the lack of availability of MIL Spec. surface mountable components. Therefore, if one is to realise the benefits of SMT, manufacturing processes must be developed that allow inserted components to be mounted on the same printed wiring board (PWB) with surface mount components (SMCs). Honeywell's Ordnance Division has developed manufacturing processes which allow SMCs to be mounted on both sides of the PWB and inserted components to be mounted on one side of the same PWB. The surface mount solder reflow and wave soldering are performed in a single‐step solder system. This simplifies and reduces the number of manufacturing process steps for this type of surface mount assembly (SMA). This paper describes three major types of SMAs and their complexity levels. Definitions of the SMA types and complexity levels are necessary for selecting production equipment and developing SMA processes. Assembly process limitations are directly related to the SMA type and complexity level. Layout guidelines and processes from solder deposition to cleaning are discussed. Full scale engineering development (FSED) hardware has been fabricated using the single‐step solder process for SMAs with both SMCs and inserted components on the same PWB. The single‐step solder process offers an excellent solution to fabricating electronic assemblies where SMCs and inserted components are mounted on the same PWB. Plans to expand and enhance the first generation SMA fabrication processes to accommodate higher complexity levels are discussed.

A general introduction is given to surface mounted devices, processes and machinery, followed by Mullard Electronic Assemblies Division's experience and a description of practical assemblies using surface mounted devices. Thoughts of future possibilities and requirements of substrate systems for the advancement of surface mounted assemblies are also presented.

The technology of printed circuit boards suitable for surface mount assembly is discussed with reference to solder mount tolerances and board finishing. Some design features which aid the production of reliable assemblies are described. The importance of preconditioning surface mount components with the soldering conditions to be utilised during the assembly process is emphasised. Some data which show the suitability of both SOIC and small PLCC packaged components, which have been vapour phase reflow soldered, are given. The reliability for long‐life applications of surface mount components and assemblies has not been demonstrated in general as yet and all manufacturers of such assemblies must validate their own assembly methods and components.

Fine pitch (0.4 mm) surface mount assembly studies were conducted with several lead‐free solder pastes formulated with both traditional RMA (∼6% residue level) and low residue (1%) flux vehicles. The lead‐free solder alloys evaluated included the two baseline eutectic binary alloys, Sn‐Bi and Sn‐Ag, and three new lead‐free solder compositions: (1)91.8Sn–4.8Bi–3.4Ag (wt%) developed at Sandia Laboratories, (2) 77.2Sn–20ln–2.8Ag (Indalloy 227) developed at Indium Corporation of America and (3) 96.2Sn–2.5Ag–0.8Cu–0.5Sb (Castin) provided by AIM, Inc. The basic physical properties pertinent to assembly performance (melting temperature and wetting behaviour) were determined for each of the new alloys. Assembly performance was assessed as a function of circuit board surface finishes, thermal reflow profiles and solder paste flux composition. The feasibility of 0.4 mm pitch assembly was established with each of the lead‐free solder alloys investigated. No issues particular to the combined use of low residue flux vehicles and lead‐free solder powders were identified. The circuit board laminates did not suffer any thermal degradation effects (reflow was performed in an inert atmosphere). All lead‐free solders, compared with the Sn‐Pb eutectic solder, exhibited reduced spreading on the circuit board lands after reflow. It was concluded that the performance of the new solder formulations is adequate for surface mount applications. Further differentiation among these solders will have to be based on their long‐term reliability performance. These studies are currently under way.

In the last decade through‐hole mounting to printed wiring boards has matured and people now have the tools to diagnose and correct any solderability problems which might arise. Such is not the case with surface mount soldering technology. In surface mount the connections are smaller and are often hidden from view. Therefore when a solderability problem does occur it may never be known until the assembly fails. The solution to the situation is to understand the nature of the problems and provide assurance that they will not occur during assembly soldering. This paper is structured in two parts. The first details the types of solderability problems unique to surface mounting. Examples of these problems will be shown and discussed with reference to solder joint life. The second part of the paper discusses the solderability testing of surface mount devices and printed wiring boards intended for surface mounting. This discussion will concentrate on the new quantitative solderability test methods being developed in this company's laboratory for leadless devices and printed wiring boards. As part of this development, new solderability criteria have been defined which reflect the unique problems associated with surface mounting.

Surface mount technology (SMT) is being increasingly used in printed circuit board (PCB) assembly. The reduced lead pitch of surface mount components coupled with their increased lead count and packing densities have made it imperative that automated placement methods be used. However, the SMT placement process is often a bottleneck in surface mount manufacturing. A reduction in placement time in SMT will enhance throughput and productivity. This paper describes the design and development of a prototype expert system based approach which identifies ‘near’ optimal placement sequences for surface mount PCBs in (almost) realtime. The software structure used integrates a knowledge based system with an optimisation module. PROLOG is the language used in this research. The system was rigorously validated and tested. Ideas for further research are also presented.

Non‐corrosive rosin fluxes have historically been used for telephone communications assemblies because they provide a measure of reliability even if the flux is not totally removed from the assembly. While cleaning is not always necessary from a reliability standpoint, testing issues, product appearance, operating performance and customer requirements must also be considered when making the decision whether or not to clean. As the electronics industry packages more and more functionality on less and less real estate, soldering yields need to increase in order for the assembly process to remain profitable. This requires not only attention to the product's design for manufacturing but it may also require aggressive fluxes to be used in the assembly process. When aggressive fluxes are employed, the necessity for cleaning is greatly increased. The particular combination of flux and cleaning option depends on product design, process capabilities, end point requirements, and environmental considerations. Pending restrictions on the production and use of chlorofluorocarbons (CFCs), and the potential for tighter controls on chlorinated solvents and aqueous detergent effluents, are certain to add to the cost of standard processes. For these reasons alternative cleaning processes have been explored. The evaluation and subsequent use of water soluble flux with ‘water only’ cleaning, terpene cleaning of rosin flux residues, low solids flux ‘no‐clean’ wave soldering and ‘no‐clean’ assembly using reflowed rosin based solder pastes within AT&T are reviewed. A user's assessment of aqueous and semi‐aqueous cleaning is presented which indicates that there are acceptable alternatives to CFCs.

The potentially highly automated process of surface mounting electronic components directly onto a substrate or printed circuit board possesses a very weak link. Component movement subsequent to placement and before or during solder reflow leads to defect conditions such as tombstoning or rotational misalignment. This work investigates the feasibility of replacing this ‘weak’ assembly step(s) with ultrasonics. The selection and modification of suitable ultrasonic equipment is described as in the bonding of chip components onto PCBs. Reliability analysis of the resultant bonds along with bond quality in terms of shear strength and appearance under scanning electron microscope and optical microscope is studied. The results show that, with certain preferred directions of ultrasonic weld, weld preload and weld time bond strengths obtained compare very favourably with those achieved with the present surface mount technology reflow process, hence establishing the feasibility of ultrasonics for this application.

Over the past few years there has been increasing utilisation of higher density surface mounting on printed wiring boards. As components and pads decrease in size, the topography of the solder mask relative to the conductors becomes an important solderability issue. There exists convincing evidence that thinner, more conformal solder mask geometries improve soldering yields of both stencilled and wave soldered surface mount components. In order to provide the solder mask coverage required for improved assembly performance, the authors critically compared several commercially available solder mask coating technologies. The coating methods were appraised according to both assembly and printed wiring board manufacturing criteria. Within this programme, seven liquid photoimageable solder masks were also evaluated. The materials were rated according to their final cured properties (electrical, mechanical, chemical performance), their manufacturability in the printed wiring board manufacturing process (maximum throughput, major defects, etc.) and their performance in assembly operations (soldering yields, propensity to ‘solder ball’ formation, white residues, scratches, etc.). The information obtained was used to choose a solder mask strategy which would not only improve assembly efficiency but also increase PWB manufacturing yields and flexibility.

Surface Mounting is shown to be the fourth generation of electronic interconnection technology. It has several facets and is seen differently from various viewpoints in the assembly industry. A review of published papers shows that the subject grew during the 1970s with no single inventor and as a result of numerous developments which are now combining into a coherent technology with important compatibility with other recent innovations.