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It is a huge technical and engineering challenge to realize the precise assembly of thousands of large optics in high power solid-state laser system. Using the 400-mm aperture-sized transport mirror as a case, this paper aims to present an intelligent numerical computation methodology for mounting performance analysis and modeling of large optics in a high-power laser system for inertial confinement fusion (ICF).

Fundamental principles of modeling and analysis of the transport mirror surface distortion are proposed, and a genetic algorithm-based computation framework is proposed to evaluate and optimize the assembly and mounting performance of large laser optics.

The stringent specifications of large ICF optics place very tight constraints upon the transport mirror’s assembly and mounts. The operational requirements on surface distortion [peak-to-valley and root mean square (RMS)] can be met as it is appropriately assembled by the close loop of assembly-inspection-optimization-fastening. In the end, the experimental study validates the reliability and effectiveness of the transport mirror mounting method.

In the assembly design and mounting performance evaluation of large laser optics, the whole study has the advantages of accurate evaluation and intelligent optimization on nano-level optical surface distortion, which provides a fundamental methodology for precise assembly and mounting of large ICF optics.

Surface Mounting is shown to be the fourth generation of electronic interconnection technology. It has several facets and is seen differently from various viewpoints in the assembly industry. A review of published papers shows that the subject grew during the 1970s with no single inventor and as a result of numerous developments which are now combining into a coherent technology with important compatibility with other recent innovations.

Implementing surface mount technology (SMT) into military systems has not progressed as rapidly as expected. One of the major reasons is the lack of availability of MIL Spec. surface mountable components. Therefore, if one is to realise the benefits of SMT, manufacturing processes must be developed that allow inserted components to be mounted on the same printed wiring board (PWB) with surface mount components (SMCs). Honeywell's Ordnance Division has developed manufacturing processes which allow SMCs to be mounted on both sides of the PWB and inserted components to be mounted on one side of the same PWB. The surface mount solder reflow and wave soldering are performed in a single‐step solder system. This simplifies and reduces the number of manufacturing process steps for this type of surface mount assembly (SMA). This paper describes three major types of SMAs and their complexity levels. Definitions of the SMA types and complexity levels are necessary for selecting production equipment and developing SMA processes. Assembly process limitations are directly related to the SMA type and complexity level. Layout guidelines and processes from solder deposition to cleaning are discussed. Full scale engineering development (FSED) hardware has been fabricated using the single‐step solder process for SMAs with both SMCs and inserted components on the same PWB. The single‐step solder process offers an excellent solution to fabricating electronic assemblies where SMCs and inserted components are mounted on the same PWB. Plans to expand and enhance the first generation SMA fabrication processes to accommodate higher complexity levels are discussed.

Low relative humidity (RH) effect surface mount devices in numerous ways. The smaller size (0201) capacitor and resistor start wasting when RH is low. Due to low RH, electrostatic charges built-up on the surface of surface mount devices (SMDs) and component’s reel. The positive charged SMDs stick with the negatively charged reel tape and are wasted. This paper comprehensively explores the environmental effects on 0201 size surface mount devices during mounting process. Different type and size of surface mount devices are tested in low and desired RH to validate the effectiveness of the proposed approach. This paper will also highlight high electrostatic discharge (ESD) due to low RH which can be detrimental for small size surface mount devices. The experimental and graphical illustrations will stipulate the results of success rate for mounting components. The effect on ESD, subsequently varying temperature and humidity will also be analyzed.

In this paper, 0201 SDMs will be considered for analysis. The surface mount technology (SMT) plant temperature and humidity has been varied to examine the properties of small size SMDs. Total 5 hours production data are collected from Laptop motherboard production environment. This approach is applicable to all SMT environment.

The authors reduced the wastage of 0201 chip size resistor and capacitor. Total 11 components are selected of this size, and there success rate is observed during mounting. These components are first observed in harsh environment where the temperature is first set to 20ºC and RH is set to 25 per cent. The success rate of these components is very low due to component’s wastage. When the plant temperature is set to 25ºC and RH is set to 45 per cent, the success rate of mounting increased up to 100 per cent. A single component placement success rate with respect to RH is observed for one month. The results are shown in Table IV. It can be seen that the success rate is near 100 per cent when RH and temperature is maintained in production environment. To eliminate the ESD build-up in material and equipment in manufacturing environment humidification is a very effective way. When the RH is kept to 45 per cent, the moisture content of the air is a natural conductor and earths any ESD in environment.

Experimental data have been obtained from Laptop motherboard manufacturing process to validate the effectiveness of proposed approach.

The popular reflow day was repeated at Henley and commenced with Mike Judd giving an overview of current reflow techniques.

Thermal characterisation of surface mount devices (SMDs) has become a growing concern as these components have increased in use—a situation aggravated by the lack of accepted industry standards for making thermal measurements. This paper attempts to provide better understanding of thermal resistance terminology, and to summarise some of the existing problems with current standards and common practices. A defined methodology for obtaining SMD thermal characteristics is proposed, involving measurement by vendors and confirmation by users, and suitable for use in meeting application‐oriented requirements. The importance of providing a clear and complete set of test condition information is also emphasised.

Long‐term fatigue life estimation for solder joints of surface mount IC packages is studied through elasto‐plastic stress analysis and temperature cycling tests. Strain on the solder joint induced by thermal expansion mismatch between package and substrate has been analysed by considering elasto‐plastic behaviour of the solder and by treating leads as rigid frames. Validity of the analysis has been confirmed by stiffness measurement of the soldered leads. Dynamic shear stress‐strain relationships of type 60Sn/40Pb solder are obtained as a function of temperature and frequency using hollow solder specimens of 15 mm in diameter and hollow solder joint specimens with the same diameter in the temperature range of −60°C to 150°C with frequencies of 0.01 Hz and 0.3 Hz. Fatigue tests are carried out for the solder specimens and the solder joint specimens under shear strain control and for the solder joints of the real IC packages under displacement control. All fatigue tests are conducted at room temperature with a frequency of 1 Hz. Fatigue test data of solder, solder joint and the solder joints of real IC packages fall in the same scatter band in the stra'un‐cycles to failure diagram. A fatigue life estimation model for solder joints of surface mount IC packages is proposed, which is derived by combining the strain calculated by the elasto‐plastic analysis and the fatigue data. To apply the proposed model to IC packages, the temperature cycling test between −55°C and +150°C is performed for two IC packages with different lead designs mounted on two different substrates (ceramics and glass‐epoxy). It is found that the fatigue life of solder joints by the temperature cycling test can be estimated by the proposed fatigue life estimation model. The proposed method is viable because it has sufficient accuracy with a cost of less than 1/100 when compared with the finite element method.

Surface mount technology (SMT) is being increasingly used in printed circuit board (PCB) assembly. The reduced lead pitch of surface mount components coupled with their increased lead count and packing densities have made it imperative that automated placement methods be used. However, the SMT placement process is often a bottleneck in surface mount manufacturing. A reduction in placement time in SMT will enhance throughput and productivity. This paper describes the design and development of a prototype expert system based approach which identifies ‘near’ optimal placement sequences for surface mount PCBs in (almost) realtime. The software structure used integrates a knowledge based system with an optimisation module. PROLOG is the language used in this research. The system was rigorously validated and tested. Ideas for further research are also presented.

Telecom equipment is subject to thermal cycles caused by both variations in temperature between day and night and variations in the telephone traffic. To simulate such thermal excursions, accelerated thermal cycle testing between — 10°C and 100°C has been established as a standard method within Ericsson Telecom. Thermal cycle tests have been carried out for frequencies ranging from one cycle per day to 30 cycles per hour in order to cover the different thermal excursions that occur in telecom equipment. It has been found that the life of a surface mounted PWB assembly can be predicted from the accelerated testing results using a frequency modified Coffin‐Manson relation. Factors which influence the fatigue life of solder joints such as solder material, compliant leads, compliant surface layers and mismatch between package and board are discussed. Based on results from accelerated testing it is suggested that the optimal PWB design for leadless ceramic chip carriers should be a moderate TCE matching combined with a compliant surface layer.

Alloy 42 and, similarly, Kovar were developed to provide metallic feed‐throughs from the interior of ceramic components to the exterior. The low coefficient of thermal expansion (CTE) of ceramic needs to be almost matched by the feed‐through metal to allow reliable hermetically sealed connections. For this purpose these alloys have served very well. However, because of its wide‐spread use for military applications, for which component hermeticity has been required, as well as because of the easier attachment of low‐CTE die to low‐CTE lead frames, Alloy 42 has found its way into plastic components with often disastrous results. When surface mount solder joints connect materials with different CTEs, global thermal expansion mismatches result. Also, if the materials to which the solder bonds have CTEs that differ from the CTE of solder, local thermal expansion mismatches result. These thermal expansion mismatches are the cause of most SM solder joint failures. Alloy 42 and Kovar not only cause significant global and local thermal expansion mismatches, but are inherently more difficult to solder because of the low solubility of nickel and iron, the main constituents of these alloys, in tin. Pull tests of solder joints show that under the best of circumstances a solder joint that includes an Alloy 42 or Kovar surface is only half as strong as one made to copper surfaces.