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Successive Approximation Register-Analog to Digital Converter (SAR-ADC) has been achieved notable technological advancement since the past couple of decades. However, it’s not accurate in terms of size, energy, and time consumption. Many projects proposed to make it energy efficient and time-efficient. Such designs are unable to deliver two parallel outputs.

To this end, this study introduced an ultra-low-power circuitry for the two blocks (bootstrap and comparator) of 11-bit SAR-ADC. The bootstrap has three sub-parts: back-bone, left-wing and right-wing, named as bat-bootstrap. The comparator block has a circuitry of the two comparators and an amplifier, named as comp-lifier. In a bat-bootstrap, the authors plant two capacitors in the back-bone block to avoid the patristic capacitance. The switching system of the proposed design highly synchronized with the short pulses of the clocks for high accuracy. This study simulates the proposed circuits using a built-in Cadence 90 nm Complementary Metal Oxide Semiconductor library.

The results suggested that the response time of two bat-bootstrap wings and comp-lifier are 80 ns, 120 ns, and 90 ns, respectively. The supply voltage is 0.7 V, wherever the power consumption of bat-bootstrap, comp-lifier and SAR-ADC are 0.3561µW, 0.257µW and 35.76µW, respectively. Signal to Noise and Distortion Ratio is 65 dB with 5 MHz frequency and 25 KS/s sampling rate. The input referred noise of the amplifier and two comparators are 98µVrms, 224µVrms and 224µVrms, respectively.

Two basic circuit blocks for SAR-ADC are introduced, which fulfill the duality approach and delivered two outputs with highly synchronized clock pulses. The circuit sharing concept introduced for the high performance SAR-ADCs.

The design method of high-resolution capacitor arrays was proposed to improve the precision of successive approximation register (SAR) analog-to-digital converters (ADCs) without calibration and optimize the circuit area.

According to calculation of equivalent series capacitors and change of voltage at the comparator input node, two three-stage structures of capacitor arrays and a general design flow of the multi-stage capacitor arrays were presented. Non-ideal factors on the capacitor arrays were analyzed, and the applications of the two structures were explained based on the capacitor mismatch.

A multi-stage capacitor array for 16-bit SAR ADCs was implemented. The simulation result shows that its nonlinear error was less than 0.3LSB with no gain error and the sampling capacitance accounted for 92.42% of the total capacitance. Effects of capacitive parasitic and mismatch on capacitor arrays were confirmed.

The proposed method focused on capacitor arrays design of high-resolution SAR ADCs. It effectively reduced nonlinear errors, improved SNR and optimized the area of SAR ADCs. The design method was suitable for SAR ADCs with different resolutions to improve their precision.

Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC.

A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration.

The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms.

The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

The purpose of this paper is to present analysis of the feedback predictive encoder-based analog-to-digital converter (ADC).

The use of feedback predictive encoder-based ADCs presents an alternative to the traditional two-stage pipeline ADC by replacing the input estimate producing first stage of the pipeline with a predictive loop that also produces an estimate of the input signal.

The overload condition for feedback predictive encoder ADCs is dependent on input signal amplitude and frequency, system gain and filter order. The limitation on the practical usable filter order is set by limit cycle oscillation. A boundary condition is defined for determination of maximum usable filter order. In a practical implementation of the predictive encoder ADC, the time allocated to the key functions of the gain stage and loop quantizer leads to optimization of the power consumption.

A practical switched capacitor implementation of the predictive encoder-based ADC is proposed. The power consumption of key circuit blocks is investigated.

This paper presents a methodology to optimize the bandwidth of predictive encoder ADCs. The overload and stability conditions may be used to determine the maximum input signal bandwidth for a given loop quantizer. Optimization of power consumption based on the allocation of time between the gain stage and the successive approximation register ADC operation is investigated. The lower bound of power consumption for this architecture is estimated.

As technology advances the demand for an analog-to digital converter has increased, as every application demands a converter as per its parameters. Currently, work is done on improvement of data converters at three levels of design – architectural, circuit and physical level. This paper aims to review the work done in the field of analog-to-digital converters (ADCs) at architectural and circuit level and discusses the achievements in this field. Furthermore, a new architecture is proposed, which works at higher resolution and provides optimum design parameters at low power consumption.

A hybrid architecture combining the features of synthetic approximation register and sigma-delta ADC is presented. The validity of the proposed design at architectural level is verified using MATLAB SIMULINK simulations.

The design simulation was tested for a sinusoidal wave of 1 V at the test frequency of 60 Hz. The design consumes least power, and is found to yield an error of the order less than 10–3 V, thus providing highly accurate digital output.

The design is applicable in many applications including biomedical systems, Internet-of-Things and earthquake engineering. This architecture can be further optimized to obtain better performance parameters.

There are many types of the ADCs implemented in the mobile and wireless devices. Most of these devices are battery operated and operational at low input voltage. SAR ADC is popular for its low power operations and simple architecture. Scientists are still working to make its working faster under the same low power area. There are many SAR-ADC implemented in the past two decades, but still, there is a big room for dual SAR-ADC.

The authors are presenting a dual SAR-ADC with a smaller number of components and blocks. The proposed ultra-low-power circuit of the SAR-ADC consists of four major blocks, which include Bee-bootstrap, Spider-Latch dual comparator, dual SAR-logic and dual digital to analog converter. The authors have used the 90-nm CMOS library for the construction of the design.

The power breaks down of the comparator are dramatically improved from 0.006 to 0.003 uW. The ultimate design has 5 MHz operating frequency with 25 KS/s sampling frequency. The supply voltage is 1.2 V with 35.724 uW power consumption. Signal-to-noise and distortion ratio and spurious-free dynamic range are 65 and 84 dB, respectively. The Walden's figure of merits calculated 7.08 fj/step.

The authors are proposing two-in-one circuit for SAR-ADC named as “dual SAR-ADC”, which obeys the basic equation of duality, derived and proved under the heading of proposed solution. It shows a clear difference between the performance of two circuit-based ADC and one dual circuit ADC. The number of components is reduced by sharing the work load of some key components.

With increasing employment of ethnic minority (EM) workers from different nationalities to mitigate the growing demand for a construction workforce, the safety and health problems of these workers have become a significant concern. The purpose of this paper is to identify and rank according to severity the safety and health-related problems confronted by EM construction workers.

Grounded theory approach was employed to construct the main categories and subcategories of the construction safety and health problems of EM workers. A two-round Delphi survey of 18 experts, who are highly experienced in managing EM workers, was conducted to rank the relative severity of the identified safety and health problems.

A total of 14 subcategories and 4 categories of construction safety and health problems of EM workers were identified. Among the 14 subcategories, the most urgent and serious ones were insufficient safety materials and training in their native language, insufficient safety staff from EM origin, and safety communication barriers. In addition, safety and health problems at the corporate and governmental levels are also worth paying attention.

This study contributes to the update on the existing body of knowledge on safety and health problems encountered by EM construction workers and revelation of their peculiar situation in Hong Kong. Findings of the study will be of value to various stakeholders in formulating safety and health measures for EM construction workers.

The purpose of this paper is to explore international buyer–supplier relationships in an emerging developing country context. The study examines a number of factors derived from internationalization process (IP) theory and their impacts in a novel research setting. The relational variables of trust and commitment, and their drivers, are integrated into a model examining importers’ perspectives of their supplier relationships.

This study applied a sequential methodological approach. Initially, a conceptual framework was developed from qualitative research and then quantitatively validated using structural equation modeling (SEM). The data for this study were collected conducting in-depth interviews and survey questionnaires. For empirical validation, the SEM technique was applied to assess the proposed model.

Importing firm managers perceived that the commitment of their suppliers bolstered their trust in the relationship, this contrasts with the conventional contention of a reverse relationship. The findings confirm cultural similarity facilitates communication, leading to increased knowledge and experience of importers, thereby contributing to an enhanced commitment to build trust in the relationship.

The conceptual framework developed in this study provides a direction to manage and enhance understanding of IP and relationship outcome. The findings have strategic implications for practicing managers in developing and supporting their importer–foreign supplier relationships.

This study is unique in assessing as well as validating key constructs of IP theory in an international exchange (importer–supplier) relationship. The study offers completely a new insight in relation to applying IP theory’s relational perspectives.