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Article
Publication date: 9 August 2011

Ashwani K. Rana, Narottam Chand and Vinod Kapoor

The purpose of this paper is to develop analytical model for gate tunneling current for an ultra‐thin gate oxide n‐channel MOSFET with inevitable nano scale effects (NSE).

Abstract

Purpose

The purpose of this paper is to develop analytical model for gate tunneling current for an ultra‐thin gate oxide n‐channel MOSFET with inevitable nano scale effects (NSE).

Design/methodology/approach

A computationally efficient model for gate tunneling current for an ultra‐thin gate oxide n‐channel MOSFET in nano scale is presented. The model predictions are compared with the two‐dimensional Sentaurus device simulation.

Findings

Good agreement between the model and experimental data was obtained. The model also shows good agreement when compared with Sentaurus simulation and available model. It is observed that neglecting NSE may lead to large error in the calculated gate tunneling current. The findings provide a guideline to the severity of NSE from the point of view of standby power consumption. It is found that temperature and substrate bias have almost negligible effect on gate tunneling current. The gate tunneling current variation with gate bias, gate oxide thickness and source/drain overlap region have also been assessed.

Research limitations/implications

The present work is concentrated only on the gate leakage current and is useful for gate leakage analysis of the circuits.

Practical implications

The model so developed is conceptually simple, numerically efficient and can be used for circuit simulator.

Originality/value

NSE are considered while modeling the gate tunneling current through nano scale n‐channel MOSFET.

Details

Multidiscipline Modeling in Materials and Structures, vol. 7 no. 2
Type: Research Article
ISSN: 1573-6105

Keywords

Article
Publication date: 30 January 2018

Saeid Masoumi, Hassan Hajghassem, Alireza Erfanian and Ahmad Molaei Rad

Smart sensors based on graphene field effect transistor (GFET) and biological receptors are regarded as a promising nanomaterial that could be the basis for future generation of…

Abstract

Purpose

Smart sensors based on graphene field effect transistor (GFET) and biological receptors are regarded as a promising nanomaterial that could be the basis for future generation of low-power, faster, selective real-time monitoring of target analytes and smaller electronics. So, the purpose of this paper is to provide details of sensors based on selective nanocoatings by combining trinitrotoluene (TNT) receptors (Trp-His-Trp) bound to conjugated polydiacetylene polymers on a graphene channel in GFET for detecting explosives TNT.

Design/methodology/approach

Following an introduction, this paper describes the way of manufacturing of the GFET sensor by using investigation methods for transferring graphene sheet from Cu foil to target substrates, which is functionalized by the TNT peptide receptors, to offer a system which has the capability of answering the presence of related target molecules (TNT). Finally, brief conclusions are drawn.

Findings

In a word, shortly after graphene discovery, it has been explored with a variety of methods gradually. Because of its exceptional electrical properties (e.g. extremely high carrier mobility and capacity), electrochemical properties such as high electron transfer rate and structural properties, graphene has already showed great potential and success in chemical and biological sensing fields. Therefore, the authors used a biological receptor with a field effect transistor (FET) based on graphene to fabricate sensor for achieving high sensitivity and selectivity that can detect explosive substances such as TNT. The transport property changed compared to that of the FET made by intrinsic graphene, that is, the Dirac point position moved from positive Vg to negative Vg, indicating the transition of graphene from p-type to n-type after annealing in TNT, and the results show the bipolar property change of GFET with the TNT concentration and the possibility to develop a robust, easy-to-use and low-cost TNT detection method for performing a sensitive, reliable and semi-quantitative detection in a wide detection range.

Originality/value

In this timeframe of history, TNT is a common explosive used in both military and industrial settings. Its convenient handling properties and explosive strength make it a common choice in military operations and bioterrorism. TNT and other conventional explosives are the mainstays of terrorist bombs and the anti-personnel mines that kill or injure more than 15,000 people annually in war-torn countries. In large, open-air environments, such as airports, train stations and minefields, concentrations of these explosives can be vanishingly small – a few parts of TNT, for instance, per trillion parts of air. That can make it impossible for conventional bomb and mine detectors to detect the explosives and save lives. So, in this paper, the authors report a potential solution with design and manufacture of a GFET sensor based on a biological receptor for real-time detection of TNT explosives specifically.

Details

Sensor Review, vol. 38 no. 2
Type: Research Article
ISSN: 0260-2288

Keywords

Article
Publication date: 6 March 2009

Himanshu Batwani, Mayank Gaur and M. Jagadesh Kumar

The purpose of this paper is to present an analytical drain current model for output characteristics of strained‐Si/SiGe bulk MOSFET.

Abstract

Purpose

The purpose of this paper is to present an analytical drain current model for output characteristics of strained‐Si/SiGe bulk MOSFET.

Design/methodology/approach

A physics‐based model for current output characteristics and transconductance of strained‐Si/SiGe bulk devices has been developed incorporating the impact of strain (in terms of equivalent Ge mole fraction), strained silicon thin film thickness, gate work function, channel length and other device parameters. The accuracy of the results obtained using this model is verified by comparing them with 2D device simulations.

Findings

This model correctly predicts the output characteristics, IDSVGS characteristics, transconductance and output conductance of the strained‐Si/SiGe MOSFET and demonstrates a significant enhancement in the drain current of the MOSFET with increasing strain in the strained‐Si thin film, i.e. with increasing equivalent Ge concentration in the SiGe bulk.

Research limitations/implications

Can be implemented in a SPICE like simulator for studying circuit behaviour containing strained‐Si/SiGe bulk MOSFETs.

Practical implications

The model discussed in this paper can be easily implemented in a circuit simulator and used for the characterization of strained silicon devices. This complements the recent trend of investigation of new materials and device structures to maintain the rate of advancement in VLSI technology.

Originality/value

This paper presents, for the first time, a compact surface potential‐based analytical model for strained‐Si/SiGe MOSFETs which predicts the device characteristics reasonably well over their range of operation.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, vol. 28 no. 2
Type: Research Article
ISSN: 0332-1649

Keywords

Article
Publication date: 26 July 2013

Joon Huang Chuah and David Holburn

The purpose of this paper is to design a very low‐noise transimpedance amplifier (TIA) for a novel multi‐pixel CMOS photon detector which performs secondary electron (SE…

1084

Abstract

Purpose

The purpose of this paper is to design a very low‐noise transimpedance amplifier (TIA) for a novel multi‐pixel CMOS photon detector which performs secondary electron (SE) detection in the scanning electron microscope (SEM).

Design/methodology/approach

The TIA, which is implemented with three‐stage push‐pull inverters, is optimised using a nomograph technique developed in MATLAB. SPICE simulations are conducted to verify the results generated from MATLAB. Important performance figures are obtained experimentally and these measurements are compared with simulation results.

Findings

A low‐noise TIA fabricated in a standard 0.35 μm CMOS technology was tested. Experimental results obtained show that the TIA connected to a photodiode with a junction capacitance of 0.8 pF can carry out its task effectively with a transimpedance gain of 126.9 dBΩ, a bandwidth of 9.8 MHz, an input‐referred noise of 2.50×10−13 A/√Hz and an SNR of 12.8. The power consumption of the TIA was 49.3 mW. These encouraging results have exhibited the potential of the circuit for use in the CMOS photon detector.

Originality/value

This paper presents a low‐noise transimpedance amplifier that is highly suitable to be used as a critical constituent block for the CMOS photon detector which aims to take over the role of photomultiplier tube in SE detection in the SEM. Solid‐state approaches have recently been reinvigorated for improving certain aspects of SE detection in scanning electron microscopy and this work has supported and contributed to the trend.

Article
Publication date: 31 July 2009

K.G. Verma, B.K. Kaushik and R. Singh

Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The purpose of this paper is to provide a comprehensive…

Abstract

Purpose

Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The purpose of this paper is to provide a comprehensive overview of types and sources of all aspects of interconnect process variations.

Design/methodology/approach

The impacts of these interconnect process variations on circuit delay and cross‐talk noises along with the two major sources of delays – parametric delay variations and global interconnect delays – have been discussed.

Findings

Parametric delay evaluation under process variation method avoids multiple parasitic extractions and multiple delay evaluations as is done in the traditional response surface method. This results in significant speedup. Furthermore, both systematic and random process variations have been contemplated. The systematic variations need to be experimentally modeled and calibrated while the random variations are inherent fluctuations in process parameters due to any reason in manufacturing and hence are non‐deterministic.

Originality/value

This paper usefully reviews process variation effects on very large‐scale integration (VLSI) interconnect.

Details

Microelectronics International, vol. 26 no. 3
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 1 January 2008

Jian‐hong Yang, Gui‐fang Li and Hui‐lan Liu

Choosing suitable high‐K gate dielectrics to reduce the off‐state leakage (Ioff) by edge direct tunneling mechanism, demonstrating that the decreased Ioff increase significantly…

Abstract

Purpose

Choosing suitable high‐K gate dielectrics to reduce the off‐state leakage (Ioff) by edge direct tunneling mechanism, demonstrating that the decreased Ioff increase significantly when the gate dielectrics permittivity are above 25. The purpose of this paper is to report that HfSiON and HfLaO are promising gate dielectrics.

Design/methodology/approach

The off‐state gate current, drain current, and substrate current are investigated. The IdVgs characteristics for the 50 and 90 nm NMOSFET with various gate dielectrics are studied. Edge direct tunneling current (IEDT) with various gate dielectrics including SiO2, Si3N4 and HfO2 are compared and this paper also examines the IEDT with HfSiON and HfLaO gate dielectrics.

Findings

IEDT prevails over conventional gate‐induced drain‐leakage current (IGIDL), subthreshold leakage current (ISUB), band‐to‐band tunneling current (IBTBT) and it dominates off‐state leakage current. A large increase in off‐state leakage current occurs for smaller devices due to increase in IEDT at high Vdd. Although IEDT is decreased with increase in gate dielectrics permittivity K. The authors found fringing induced barrier lowering (FIBL) which could introduce significant off‐state leakage current for K>25. Fortunately, the IEDT with HfSiON and HfLaO gate dielectrics which are two‐five orders of magnitude lower than that of SiO2, furthermore, FIBL for HfSiON and HfLaO gate dielectrics are inconspicuous. Moreover, HfLaO and HfSiON have superior electrical performance and thermal stability.

Originality/value

Both edge direct tunneling and FIBL are considered to alternate high‐K gate dielectrics for nano‐scale MOSFET.

Details

Microelectronics International, vol. 25 no. 1
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 1 January 2008

Bhavana Jharia, S. Sarkar and R.P. Agarwal

The purpose of this paper is to analyze the effects of scaling on the impact ionization and subthreshold current in submicron MOSFETs.

Abstract

Purpose

The purpose of this paper is to analyze the effects of scaling on the impact ionization and subthreshold current in submicron MOSFETs.

Design/methodology/approach

The effects of the various scaling techniques on a 100 nm device performances and the dependence of subthreshold current parameters on applied scaling technique are analyzed.

Findings

The results show that as the channel length is scaled down, multiplication factor increases slowly in the higher regime and rises rapidly in the lower regime of channel length. This result also justifies the inclusion of impact‐ionization effect on subthreshold current. The analysis shows that there is insignificant dependence of multiplication factor on the method of scaling. Similar variations in subthreshold current with channel length scaling have been observed in the analytical results for different scaling techniques.

Originality/value

The paper offers insight into the challenges of MOSFET scaling.

Details

Microelectronics International, vol. 25 no. 1
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 26 January 2010

Harikrishnan Ramiah, Tun Zainal Azni Zulkifli and Noramalia Sapiee

The purpose of this paper is to design and realize a low‐phase noise, high‐output power, and high‐tuning range, fully integrated source injection parallel coupled (SIPC)‐based…

Abstract

Purpose

The purpose of this paper is to design and realize a low‐phase noise, high‐output power, and high‐tuning range, fully integrated source injection parallel coupled (SIPC)‐based inductor‐capacitor (LC)‐quadrature voltage controlled oscillator (QVCO) covering WiMAX frequency range in 0.18‐μm deep submicron CMOS technology.

Design/methodology/approach

A pMOS based‐SIPC LC‐QVCO topology is realized with the center frequency of 2.58 GHz. On chip spiral inductor is integrated with substantial quality factor, Q coupled with underlying pattern ground shield (PGS) shielding. An enhanced tuning range is achieved by integrating the diode connected MOS‐based varactors. The CMOS‐based autonomous SIPC LC‐QVCO circuit was characterized for its output phase noise, tuning range and power spectrum response via wafer probing, utilizing a signal source analyzer (Agilent E5052 A).

Findings

A quadrature oscillator catering to the needs of local oscillator (LO) generation covering the frequency range of WiMAX is realized. The parallel coupled architecture adapts direct source coupling, bypassing the LC resonator tank and relaxes the close in phase noise up‐conversion. The design consumes 2.19 mm2 of active chip area and measures a phase noise of −114.34 dBc/Hz at 1 MHz of offset frequency with 2.67 GHz of output frequency at 0.9 V of input tuning voltage. The corresponding output power measures to be −10.1 dBm, well suited for mixer hard switching. The design is realized in one poly, six metal 0.18‐μm standard CMOS technology.

Research limitations/implications

Owing to convergence discrepancy in the analysis, a diode‐connected MOS varactor is adapted in contrary to the accumulation mode MOS varactors with superior tuning range.

Practical implications

The designed SIPC LC‐QVCO is of need in the generation of low‐phase noise, highly matched quadrature LO generation covering the WiMAX frequency range. The adapted parallel coupling also relaxes the voltage headroom limitation.

Originality/value

This paper shows how a fully integrated CMOS‐based SIPC LC‐QVCO architecture is adapted with low‐output phase noise and low voltage headroom consumption covering the WiMAX frequency range.

Details

Microelectronics International, vol. 27 no. 1
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 2 January 2018

Kavindra Kandpal and Navneet Gupta

The purpose of this paper is to present a comprehensive review on development and future trends in zinc oxide thin film transistors (ZnO TFTs). This paper presents the development…

1062

Abstract

Purpose

The purpose of this paper is to present a comprehensive review on development and future trends in zinc oxide thin film transistors (ZnO TFTs). This paper presents the development of TFT technology starting from amorphous silicon, poly-Si to ZnO TFTs. This paper also discusses about transport and device modeling of ZnO TFT and provides a comparative analysis with other TFTs on the basis of performance parameters.

Design/methodology/approach

It highlights the need of high–k dielectrics for low leakage and low threshold voltage in ZnO TFTs. This paper also explains the effect of grain boundaries, trap densities and threshold voltage shift on the performance of ZnO TFT. Moreover, it also addresses the challenges like requirement of stable p-type ZnO semiconductor for various electronic applications and high value of ZnO mobility to meet growing demand of high-definition light emitting diode TV (HD-LED TV).

Findings

This review will motivate the readers to further investigate the conduction mechanism, best alternate for gate-dielectric and the deposition technique optimization for the enhancement of the performance of ZnO TFTs.

Originality/value

This is a literature review. The technological evolution of TFT in general and ZnO TFT in particular is presented in this paper.

Details

Microelectronics International, vol. 35 no. 1
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 14 January 2014

Sari Lakkis, Rafic Younes, Yasser Alayli and Mohamad Sawan

This paper aims to give an overview about the state of the art and novel technologies used in gas sensing. It also discusses the miniaturization potential of some of these…

1585

Abstract

Purpose

This paper aims to give an overview about the state of the art and novel technologies used in gas sensing. It also discusses the miniaturization potential of some of these technologies in a comparative way.

Design/methodology/approach

In this article, the authors state the most of the methods used in gas sensing discuss their advantages and disadvantages and at last the authors discuss the ability of their miniaturization comparing between them in terms of their sensing parameters like sensitivity, selectivity and cost.

Findings

In this article, the authors will try to cover most of the important methods used in gas sensing and their recent developments. The authors will also discuss their miniaturization potential trying to find the best candidate among the different types for the aim of miniaturization.

Originality/value

In this article, the authors will review most of the methods used in gas sensing and discuss their miniaturization potential delimiting the research to a certain type of technology or application.

Details

Sensor Review, vol. 34 no. 1
Type: Research Article
ISSN: 0260-2288

Keywords

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