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The purpose of this paper is to investigate the creep properties of Sn‐0.7Cu composite solder joints reinforced with optimal nano‐sized Ag particles in order to improve the creep performance of lead‐free solder joints by a composite approach.

The composite approach has been considered as an effective method to improve the creep performance of solder joints. Nano‐sized Ag reinforcing particles were incorporated into Sn‐0.7Cu solder by mechanically mixing. A systematic creep study was carried out on nano‐composite solder joints reinforced with optimal nano‐sized Ag particles and compared with Sn‐0.7Cu solder joints at different temperatures and stress levels. A steady‐state creep constitutive equation for nano‐composite solder joints containing the best volume reinforcement was established in this study. Microstructural features of solder joints were analyzed to help determine their deformation mechanisms during creep.

The creep activation energies and stress exponents of Ag particle‐enhanced Sn‐0.7Cu lead‐free based composite solder joints were higher than those of matrix solder joints under the same stress and temperature. Thus, the creep properties of nano‐composite solder joints are better than those of Sn‐0.7Cu solder joints.

The findings indicated that nano‐sized Ag reinforcing particles could effectively improve the creep properties of solder joints. A new steady‐state creep constitutive equation of nano‐composite solder joints was established. Deformation mechanisms of Sn‐0.7Cu solder and nano‐composite solder joints during creep were determined.

The purpose of this paper is to investigate the effect of nickel-plated graphene (Ni-GNS) on the microstructure and mechanical properties of 96.5Sn3Ag0.5Cu (SAC305) lead-free solder joints before and after an electro-migration (EM) experiment.

In this paper, SAC305 solder alloy doped with 0.1 Wt.% Ni-GNS was prepared via the powder metallurgy method. A U-shaped sample structure was also designed and prepared to conduct an EM experiment. The EM experiment was carried out with a current density of 1.5 × 104 A/cm2. The microstructural and mechanical evolutions of both solder joints under EM stressing were comparatively studied using SEM and nanoindentation.

The experimental results showed that for the SAC305 solder, the interfacial intermetallic compounds (IMC) formulated a protrusion with an average height of 0.42 µm at the anode after 360 h of EM stressing; however, despite this, the surface of the composite solder joint was relatively smooth. During the stressing period, the interfacial IMC on the anode side of the plain SAC305 solder showed a continuous increasing trend, while the IMC at the cathode presented a decreasing trend for its thickness as the stressing time increased; after 360 h of stressing, some cracks and voids had formed on the cathode side. For the SAC305/ Ni-GNS composite solder, a continuous increase in the thickness of the interfacial IMC was found on both the anode and cathode side; the growth rate of the interfacial IMC at the anode was higher than that at the cathode. The nanoindentation results showed that the hardness of the SAC305 solder joint presented a gradient distribution after EM stressing, while the hardness data showed a relatively homogeneous distribution in the SAC305/ Ni-GNS solder joint.

The experimental results showed that the Ni-GNS reinforcement could effectively mitigate the EM behavior in solder joints under high current stressing. Specifically, the Ni particles that plated the graphene sheets can work as a fixing agent to suppress the diffusion and migration of Sn and Cu atoms by forming Sn-Cu-Ni IMC. In addition, the nanoidentation results also indicated that the addition of the Ni-GNS reinforcement was very helpful in maintaining the mechanical stability of the solder joint. These findings have provided a theoretical and experimental basis for the practical application of this novel composite solder with high current densities.

The purpose of this study was to investigate the changes in solder joint stress when subjected to mechanical bending. The analytical theory pertaining to the stresses in the solder joint between the components (including the molding compound, the chip and the substrate) was described, and the printed circuit board (PCB) with a discontinuity function when the PCB assembly is subjected to mechanical bending was developed. Thus, the findings reported here may lead to a better understanding of the solder joint failure based on the Physics of Failure model.

This paper discusses the analytical model for calculating the stress in solder joints, as well as presents a simulation model that can be used for calculating the strain energy density of solder joint. First, the multilayer plate theory is used in discussing the composite material for the component, including the molding compound, the silicon chip and the substrate, or the PCB, including the copper layers, the fiber and the epoxy. Finally, the complete structure of the analytical model developed as a part of this current work is presented.

For the analytical model of multilayer structures in which the interconnection layer is discrete, mechanical bending has been modeled with respect to varying silicon chip length. The analytical model that describes the stress of the outermost solder joint experiences is chosen, as this is the typical solder joint failure. The analytical model can be applied to discrete solder joints, which are evaluated by calculating the matrix form. Owing to its use of the matrix equation, the analytical model can be highly combinatorial and thus more capable of calculating the solution.

The analytical solution based on a simple concept was presented and validated using the finite element model for the stress experienced by solder joints subjected to mechanical bending. To verify that the simulation represents a real PCB case, the authors use the finite element method (FEM) to compare their case with the multilayer plate theory. Owing to the good agreement between the theory and simulation results, the authors conclude that the multilayer plate theory can be correctly applied in multilayer PCB and be used in an analytical model for the PCB assembly subjected to mechanical bending.

Owing to the good agreement between the theory and simulation results, the authors conclude that the multilayer plate theory can be correctly applied in multilayer PCB and be used in an analytical model for the PCB assembly subjected to mechanical bending.

The analytical model is validated with the FEM model and provides the way to physically examine the solder joint failure mechanism. In this paper, the analytical model is developed as a means to assess the solder joint stress subjected to mechanical bending.

The analytical model treats the solder joint as discrete and has been successfully validated against the finite element model. The complete structure model (the second analytical model) is presented to discuss the effects of varying silicon chip length on the normal stress in solder joints. When the silicon chip length exceeds to 80 per cent of the total package length, the stress of the outermost solder joint increases rapidly. The design analysis findings have suggested that the failure of the outermost solder joint subjected to mechanical bending on the PCB assembly can be reduced by analyzing the analytical model.

The transistor circuit based on Moore's Law is approaching the performance limit. The three-dimensional integrated circuit (3-D IC) is an important way to implement More than Moore. The main problems in the development of 3-D IC are Joule heating and stress. The stresses and strains generated in 3-D ICs will affect the performance of electronic products, leading to various reliability issues. The intermetallic compound (IMC) joint materials and structures are the main factors affecting 3-D IC stress. The purpose of this paper is to optimize the design of the 3-D IC.

To optimize the design of 3-D IC, the numerical model of 3-D IC was established. The Taguchi experiment was designed to simulate the influence of IMC joint material, solder joint array and package size on 3-D IC stress.

The simulation results show that the solder joint array and IMC joint materials have great influence on the equivalent stress. Compared with the original design, the von Mises stress of the optimal design was reduced by 69.96 per cent, the signal-to-noise ratio (S/N) was increased by 10.46 dB and the fatigue life of the Sn-3.9Ag-0.6Cu solder joint was increased from 415 to 533 cycles, indicating that the reliability of the 3-D IC has been significantly improved.

It is necessary to study the material properties of the bonded structure since 3-D IC is a new packaging structure. Currently, there is no relevant research on the optimization design of solder joint array in 3-D IC. Therefore, the IMC joint material, the solder joint array, the chip thickness and the substrate thickness are selected as the control factors to analyze the influence of various factors on the 3-D IC stress and design. The orthogonal experiment is used to optimize the structure of the 3-D IC.

The purpose of this paper is to investigate the effect of titanium nitride (TiN) on microstructure and composition of 96.5Sn3Ag0.5Cu (SAC305) lead-free solder joints under a large temperature gradient.

In this paper, SAC305 lead-free composite solder containing 0.05 Wt.% TiN was prepared by powder metallurgy method. A temperature gradient generator was designed and the corresponding samples were also prepared. The microstructural evolution, internal structure and elemental content of SAC305 and SAC305/TiN solder joints before and after thermal loading were comparatively studied.

The experimental results show that the addition of the TiN reinforcing phase can effectively inhibit the diffusion and migration of copper atoms and, therefore, affect the distribution of newly formed Cu-Sn IMC in solder joints under the condition of thermal migration (TM). Compared with the SAC305 solder joint, the interconnection interface and internal structure of the composite solder joint after 600 h of TM are also relatively complete.

The TiN reinforcing phase is proven effective to mitigate the TM behavior in solder joints under thermal stressing. Specifically, based on the observation and analysis results of microstructure and internal structure of composite solder joint, the TiN particle can change the temperature gradient distribution of the solder joint, so as to suppress the diffusion and migration of Sn and Cu atoms. In addition, the results of Micro-CT and compositional analysis also indicate that the addition of TiN reinforcement is very helpful to maintain the structural integrity and the compositional stability of the solder joint. Different from other ceramic reinforcements, TiN has good thermo- and electro-conductivity and the thermal-electrical performance of composite solder will not be significantly affected by this reinforcement, which is also the main advantage of selecting TiN as the reinforcing phase to prepare composite solder. This study can not only provide preliminary experimental support for the preparation of high reliability lead-free composite solder but also provide a theoretical basis for the subsequent study (such as electro-thermo distribution in solder joints), which has important application significance.

This paper presents a solder joint engineering reliability model — Solder Reliability Solutions** (SRS) — and its application to surface mount area‐array and chip‐scale assemblies. The model is validated by failure data from 33 accelerated thermal cycling tests, and test vehicles covering several generations of component, assembly and circuit board technologies and a variety of test conditions. The SRS model has been implemented as a PC‐based design‐for‐reliabilltytool that enables rapid assessment of assembly reliability in the early stages of product development.

In a printed circuit board assembly (PCBA), the coefficient of thermal expansion (CTE) mismatch between the solder joint materials has a detrimental impact on reliability. The mechanical stresses caused by the thermal changes of the assembly lead to fatigue and sometimes the failure of the solder joints. The purpose of this study is to propose a novel pad design to obtain an interrupted solder/substrate interface, to improve the PCBA reliability.

An interruption in the continuous intermetallic compound (IMC) layer of a solder joint was implemented, by the deposition of a silicone film in the pad, changing its geometry. That change allows a redistribution of stresses in the most ductile zone of the solder joint, the solder. The stress concentration at the solder/substrate interface is reduced, as well as the general state of stress at the solder joint.

A new way was developed to reduce the stress on the solder joints, caused by thermal variations, because of the different components CTEs mismatch. This new method consists of interrupting the IMC layers of the solder joint, strategically, redirecting the usual stresses to a more ductile area of the joint, the solder. This is an innovative method that allows increase the lifetime of PCBAs and the equipments.

In this study, a new pad design concept for higher solder joint reliability was developed to reduce the shear stress in the solder joints because of the CTE mismatch between all the solder joint components.

Long‐term fatigue life estimation for solder joints of surface mount IC packages is studied through elasto‐plastic stress analysis and temperature cycling tests. Strain on the solder joint induced by thermal expansion mismatch between package and substrate has been analysed by considering elasto‐plastic behaviour of the solder and by treating leads as rigid frames. Validity of the analysis has been confirmed by stiffness measurement of the soldered leads. Dynamic shear stress‐strain relationships of type 60Sn/40Pb solder are obtained as a function of temperature and frequency using hollow solder specimens of 15 mm in diameter and hollow solder joint specimens with the same diameter in the temperature range of −60°C to 150°C with frequencies of 0.01 Hz and 0.3 Hz. Fatigue tests are carried out for the solder specimens and the solder joint specimens under shear strain control and for the solder joints of the real IC packages under displacement control. All fatigue tests are conducted at room temperature with a frequency of 1 Hz. Fatigue test data of solder, solder joint and the solder joints of real IC packages fall in the same scatter band in the stra'un‐cycles to failure diagram. A fatigue life estimation model for solder joints of surface mount IC packages is proposed, which is derived by combining the strain calculated by the elasto‐plastic analysis and the fatigue data. To apply the proposed model to IC packages, the temperature cycling test between −55°C and +150°C is performed for two IC packages with different lead designs mounted on two different substrates (ceramics and glass‐epoxy). It is found that the fatigue life of solder joints by the temperature cycling test can be estimated by the proposed fatigue life estimation model. The proposed method is viable because it has sufficient accuracy with a cost of less than 1/100 when compared with the finite element method.

The coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB) materials causes a reliability issue for ball grid array type electronic packages. This makes it difficult for conventional wafer level chip scaled packaging (WLCSP) with large die to satisfy the reliability requirements. Therefore, in this study a novel solder joint protection‐WLCSP (SJP‐WLCSP) structure is proposed to overcome the reliability issue.

The SJP‐WLCSP makes use of a delaminating layer to reduce the problem of CTE mismatch. In the SJP‐WLCSP, a delaminating layer is interposed between the top layer of the chip and the bottom insulating layer of the redistribution copper metal traces. As a result, the stress on the solder joints can be released by allowing cracks to form in the delaminating layer.

To elucidate the thermo‐mechanical behaviour of tin‐lead eutectic solder joints and copper traces, a non‐linear analysis, based on a 3D finite element (FE) model, under accelerated thermal test loadings was carried out. The maximum equivalent stress/strain in the solder joints predicted by the FE simulation were found to diminish significantly when applying the delaminating layer. In addition, parametric FE analysis was also applied in this study, and based on the design concepts within this study, a robust novel SJP‐WLCSP could be achieved.

In this work, a new packaging concept with high reliability, low cost and easy fabrication was developed to reduce the shear stress in the solder joints due to the CTE mismatch between silicon chips and organic PCBs.

In this paper, some strategies taken to improve the reliability of solder joints on power devices in single device and multi‐chip packages are presented. A strategy for improving solder joint reliability by adjusting solder joint geometry, underfilling and utilization of flexible substrates is discussed with emphasis on triple‐stacked solder joints that resemble the shape of an hourglass. The hourglass shape relocates the highest inelastic strain away from the weaker interface with the chip to the bulk region of the joint, while the underfill provides a load transfer from the joints. Thermal cycling data show significant improvements in reliability when these techniques are used. The design, testing and finite‐element analyses of an interconnection structure, termed the Dimple‐Array Interconnect, for improving the solder joint reliability is also presented.