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Due to increasing density and high demands on electrical and thermal performance, modern packages require alternative chip interconnection and substrate technologies. Flip‐chip (FC) bonding is a suitable method for high interconnection densities. Compared with wire bonding and TAB, FC provides the highest contact density. This is due to the possibility of using the whole chip surface for bondpads (area bumps). In this paper, an adapted FC technology on green tape ceramic substrates was investigated. In order to reduce the substrate costs, FC bonding was performed directly on the thick film metallisation without the application of thin film technology for the upper substrate layers. Two solder bump metallurgies: PbSn95/5 and Au/Sn solder bumps were applied for fluxless FC bonding on adapted substrate metallisations. Fluxless soldering is performed by single chip bonding and requires substrates with narrow planarity tolerances. An alternative method using a wet eutectic Au/Sn solder paste on the substrate and Au bumps permits the application of substrates with standard planarity tolerances used in thick film applications. A common reflow of all chips of a multichip module is possible. First reliability results of metallurgical analysis and of the mechanical and electrical behaviour of the FC contacts after thermal cycling are presented.

Tape automated bonding (TAB) is a suitable technology for assembling ICs with a high number of l/Os. The gang bonding process usually applied requires increasing thermode forces for chips with high lead counts and narrow tolerances regarding thermode parallelism and planarity. Due to the high bonding pressure, TC bonding of Au bumps to Au‐plated tapes becomes critical for these applications. In order to avoid damage to the pad structure an inner lead bonding (ILB) process with reduced pressure is required. A tape metallisation of 0.5–1.0 µm Sn is not sufficient for a significant reduction of thermode pressure. As an alternative, the application of an eutectic Au‐Sn cushion which is deposited on top of the bumps is presented. A modified bumping process was developed for the deposition of the solder bumps. Soldering of the Au‐Sn bumps to a Au‐plated tape was performed successfully by two techniques: thermode gang bonding and laser soldering. Bond parameters and tin layer thickness were optimised. Reliability investigations by thermal ageing were performed. The special metallurgical aspects of the system were investigated with a microprobe.

The purpose of this paper is to present the experimental and simulation studies on the influence of copper pillar bump structure on flip chip packaging during reflow soldering.

In this work, solidification/melting modelling and volume of fluid modelling were used. Reflow soldering process of Cu pillar type FC was modelled using computational fluid dynamic software (FLUENT). The experimental results have been validated with the simulation results to prove the accuracy of the numerical method.

The findings of this study reveal that solder volume is the most important element influencing reflow soldering. The solder cap volume reduces as the Cu pillar bump diameter lowers, making the reflow process more difficult to establish a good solder union, as less solder is allowed to flow. Last but not least, the solder cap height for the reflow process must be optimized to enable proper solder joint formation.

This study provides a basis and insights into the impact of copper pillar bump structure on flip chip packaging during reflow soldering that will be advancing the future design of 3D stack package. This study also provides a superior visualization and knowledge of the melting and solidification phenomenon during the reflow soldering process.

The computational fluid dynamics analysis of copper pillar bump structure on flip chip packaging during reflow soldering is scant. To the authors’ best knowledge, no research has been concentrated on copper pillar bump size configurations in a thorough manner. Without the in-depth study, copper pillar bump size might have the impact of copper pillar bump structure on flip chip packaging during reflow soldering. Five design of parameter of flip chip IC package model was proposed for the investigation of copper pillar bump structure on flip chip packaging during reflow soldering.

As the demand for flip‐chip products increases, the need for low cost high volume manufacturing processes also increases. Currently solder paste printing is the wafer bumping method of choice for device pitches down to 150‐200μm. However, limitations in print quality and stencil manufacture mean that this technology is not likely to move significantly below this pitch and new methods will be required to meet the demands predicted by the technology roadmaps. This paper describes experiments conducted on carriers made from silicon for bumping of die using solder paste. An anisotropic etching process was used to generate pockets in the silicon surface into which solder paste was printed. Die were then placed against the carrier and reflowed to transfer the solder directly to the bondpads. An assessment was carried out of the potential application and limitations of this technique for device pitches at 225 and 127μm.

Indium solders are frequently used for interconnections in cooled systems because of their high ductility down to very low temperatures. Very fine contact pitches are required for hybrid mosaic radiation sensors compared with those for conventional flip‐chip technology. This paper presents solutions for bumping and bonding indium bumps based on the measured properties of indium solders in relation to the requirements of, and possibilities for, manufacture of fine pitch solder bump features.

This study aims to investigate the several parameters in wafer-level packaging (WLP) to find the most critical factor impacting the thermal fatigue life, such as the height of copper post, the height of solder bump, the thickness of chip. The FEA results indicate the height of solder bumps is the most important factor in the whole structure.

The copper post bumps with 65 µm pitch are proposed to investigate the thermal-mechanical performance of WLP. The thermal cycle simulation is used to evaluate the reliability of WLP by using finite element analysis (FEA). Taguchi method is adopted to obtain the sensitivity of parameters of three-dimension finite element model, for an optimized configuration.

It can be found that the optimal design has increased thermal fatigue life by 147% compared with the original one.

It is concluded that the finite element simulation results show outstanding thermal-mechanical performances of the proposed 65 µm pitch copper post bumps of WLP, including low plastic strain, high thermal fatigue life, which are desired for mobile device.

This paper describes effective thin‐film structure barrier metals for use as eutectic solder bumps. Shear strength and bump interconnection resistance were evaluated. The mutual diffusion in metals was investigated. Barrier metal structures —Cu/Ti,Ni/Ti and Cu/Cr—were evaluated after ageing. The Ni/Ti structure has good reliability according to ageing test results. Pd is used for improvement of solder wettability and as an oxidisation barrier. Consequently, it was concluded that a thin‐film Pd/Ni/ Ti barrier metal is suitable for use as eutectic solder bumps. The broken interfaces of the solder bumps were analysed by scanning auger electron spectrometry. In the thin‐film Cu/Ti structure, decrease in the shear strength is caused by three mechanisms, as determined from the broken interface analysis. The three mechanisms are mixed metal formation, Ti oxidisation and diffusion between barrier metals and Al. Furthermore, TCT and PCT were carried out on these eutectic solder bumps to confirm the interconnection reliability. The TCT and PCT results prove that electrical connection is stable.

The objective of this research is to address issues that relate to the assembly of Sn/Ag/Cu bumped flip chips.

Flip chips bumped with Sn/Ag/Cu bumps were assembled onto different lead‐free surface finishes at lead‐free soldering temperatures. Sensitivity to fluxes, reflow profiles, pad finishes and pad designs were all investigated and the potential consequences for assembly yields were calculated numerically.

Soldering defects, such as incomplete wetting and collapse and poor self‐centring were observed in the assemblies. Defect levels were sensitive to contact pad metallurgy and flux type, but not to flux level and reflow profile within the ranges considered. Owing to a particularly robust substrate‐pad design, defects observed in this work were limited to incomplete wetting and collapse, as well as poor self‐centering.

The scope of this work is limited to the lead‐free fluxes available at the time of research. A switch to lead‐free solder alloys in flip chip assemblies raises concerns with respect to the compatibilities of materials and the quality of soldering that is achievable. While this may be less of an issue in the case of larger area array components, such as ball grid arrays and chip scale packages, it is more of a concern for applications that use flip chips due to the smaller size of the solder spheres. Assembly yields tend to become more sensitive to the reduced collapse of the joints. More work is essential to investigate the potential benefits of more active lead‐free fluxes, both no‐clean tacky and liquid fluxes, in reducing or eliminating soldering defects.

The paper offers insights into assembly issues with Sn/Ag/Cu bumped flip chips.

Modern semiconductor technologies have advanced to the level of sophistication where the benefits of the high functional and power density, high speed, low defect rate and low wafer processing cost can seldom be fully utilised at the final equipment or even at the single packaged semiconductor component level due to the limitations of wire bonds and lead frame fan‐outs. This paper suggests a new assembly method where low‐cost contact bumps are deposited on semiconductor wafers and then the dice are reflow soldered or gang bonded to the substrate. The bumps are electroless nickel deposited and coated with a protective layer of gold. As the nickel bumps are non‐collapsible, they are better suited to Extra High Density Interconnections (EHDI) than the more usual solder bumps. The amount of solder must be accurately dispensed either on the die bumps or on the substrate bonding pads using various methods. Essential to the high volume assembly is fast pick‐and‐place operation and simultaneous soldering of all components in a reflow furnace. In certain applications bonding of the bumped device (one die at a time) can be done using reflow or thermocompression gang bonding by applying a heated thermode to the backside of the die. In this case, the bonding energy will be transferred through the die to the bumps. Tentative solder joint strength and reliability aspects are discussed. Further process and design improvements are suggested.

A new solder‐bumped flip chip land grid array (LGA) chip scale package (CSP) called NuCSP is presented in this paper. NuCSP is a minimized body size package with a rigid substrate (interposer). The design concept is to utilize the interposer to redistribute the very fine pitch peripheral pads on the solder‐bumped chip to much larger pitch area‐array pads on the printed circuit board (PCB). Using conventional PCB substrate manufacturing processes, NuCSP offers a very low‐cost package suitable for memory chips and low pin‐count application‐specific ICs (ASICs). Also, NuCSP is surface mount technology (SMT) compatible and can be joined to the PCB with a 6‐mil (0.15mm) thick 63wt %Sn‐37% Pb solder paste.