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The purpose of this paper is to present a transition detector (TD)-based radiation hardened flip-flop (TDRH-FF) for single event upset (SEU).

With SEU recovery and single event transient (SET) detector mechanism, the TDRH-FF can tolerate SEU during hold mode and generate a warning signal for architecture-level recovery during transport mode when input signal contains SET. Evaluation results show that the TDRH-FF outperforms comparable comprehensive performance.

Simulation results show that 1) the mean pulse width of the correction glitches (at full width half maximum) of TDRH-FF is less than 10 ps; 2) the area overhead of TDRH-FF is similar to the EVFERST-FF, BISER-FF and DNURHL-FF; 3) TDRH-FF has the same average power consumption as SETTOF, and moderate PDP and Ps values among these compared FFs.

In this paper, a TD-based TDRH-FF is proposed to solve the problems in the previous design. And the main contributions of the proposed TDRH-FF are summarized: Minimum size transistors are used in the proposed TD which leads to a considerable decrease in area overheads and propagation delay (resulting in an ignorable correction glitch); and compared with other radiation hardened flip-flop, TDRH-FF outperforms comparable comprehensive performance.

The purpose of this paper is to design novel hardened flip-flop using carbon nanotube field effect transistors (CNTFETs).

To design the proposed flip-flop, the Schmitt trigger-based soft error masking and unhardened latches have been used. In the proposed design, the novel mechanism, i.e. hysteresis property is used to enhance the hardness of the single event upset.

To obtain the simulation results, all the proposed circuits are extensively simulated in Hewlett simulation program with integrated circuit emphasis software. Moreover, the results of the proposed latches are compared to the conventional latches to show performance improvements. It is noted that the proposed latch shows the performance improvements up to 25.8%, 51.2% and 17.8%, respectively, in terms of power consumption, area and power delay product compared to the conventional latches. Additionally, it is observed that the simulation result of the proposed flip-flop confirmed the correctness with its respective functions.

The novel hardened flip-flop utilizing ST based SEM latch is presented. This flip-flop is significantly improves the performance and reliability compared to the existing flip-flops.

Describes Actel’s programmable technology. Early adopters of this technology, in both Europe and North America in experimental and telecommunication space programmes used these field programmable gate arrays (FPGAs) very successfully. Owing to the success of these early adopters, Actel transferred its technology to a radiation hardened wafer fab and now offers a rad hard version of its commercial product, serving the needs of the traditional government end use space market and long lifetime missions. Since the introduction of the rad hard FPGAs the industry has undergone major shifts in attitudes. While there is still a significant demand for radiation hardened devices, lower cost alternatives with a lower level of radiation tolerance are expected to exist in the majority of space programmes.

The purpose of this study is to extend a sensitivity-based reliability technique for the processors deployed in industrial drive (ID).

The processor provides flexible operation, re-configurability, and adaptable compatibility in industrial motor drive system. A sensitivity-based model allows a robust tool for validating the system design. Sensitivity is the probability of a partial failure rate for a distributed variable; sensitivity and failure rates are also complementary. Conversely, traditional power electronic components reliability estimating standards have overlooked it, and it is essential to update them to account for the sensitivity parameter. A new sensitivity-based reliability prediction methodology for a typical 32-bit microprocessor operating at 30ºC deployed in ID is presented to fill this gap. The proposed techniques are compared with the estimated processor reliability values obtained from various reliability standards using the validated advanced logistics development tool. The main contribution of this work is to provide a sensitivity extended reliability method over the conventional method directing toward improving reliability, availability, and maintainability in the design of ID.

The analysis shows that the sensitivity of the processor’s circuit increases due to increases in complexity of the system by reducing the overall mean time between failure upon comparing among conventional reliability standards.

The significance of this paper lies in the overall, sensitivity-based reliability technique for processors in comparison to the traditional reliability complexity in IDs.

With continuous scaling of digital circuit CMOS technology, the vulnerability of these circuits are significantly increasing against the soft errors. On the other hand, the effects of process variation in the electrical properties of nano-scale circuits, have introduced the statistical methods as an unavoidable choice for the soft error rate (SER) estimation. The purpose of this paper is to provide a statistical soft error rate (SSER) estimation approach for combinational circuits in the presence of process variation.

In this paper a new method is proposed for the SSER estimation of combinational circuits based on the Bayesian networks (BNs). This allows to factor the joint probability distributions over variables in a circuit graph. The distribution of the initial transient fault pulse is estimated by the pre-characterization tables. Timing signals are propagated by BN theory and the probability distribution of electrical and timing masking are calculated.

Simulation results for some benchmark circuits show that the proposed method is accurate with 3.7 percent difference with the Monte-Carlo SPICE simulation and with orders of magnitude improvement in runtime.

The proposed framework is the scheme giving the low estimation time with plausible accuracy compared to other schemes. The comparison exhibits that the designer can save its estimation time in terms of performance and complexity. The deterministic-based methods also are able to evaluate the SER of combinational circuit, yet in an unacceptable time.

Kulicke and Soffa Industries, Inc. have announced the appointment of Dr Arthur J. Schneider as Vice President of Research and Development. Dr Schneider is based in Willow Grove and reports directly to Donald R. VanLuvanee, K & S President.

The degradation of both the functional and electrical parameter performance of integrated circuits has been under investigation for a number of years. Aims to demonstrate that statistical methods may be used to determine physical changes in these devices, rather than the time‐consuming and costly procedures of physical failure analysis. In addition, draws a comparison between the functional tests and the parametric tests. The data were obtained by stressing statistical samples of TMS2114L NMOS static RAMs to varying total doses of ionizing radiation. Presents and discusses the results obtained from these tests and suggests statistical and mathematical models to estimate performance degradation.