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The purpose of this paper is to develop and apply accurate and original models to understand and analyze the effects of the fabrication temperatures on thermal-induced stress and speed performance of nano positively doped metal oxide semiconductor (pMOS) transistors.

The speed performances of nano pMOS transistors depend strongly on the mobility of holes, which itself depends on the thermal-induced extrinsic stress σ. The author uses a finite volume method to solve the proposed system of partial differential equations needed to calculate the thermal-induced stress σ accurately.

The thermal extrinsic stress σ depends strongly on the thermal intrinsic stress σ₀, thermal intrinsic strain ε₀, elastic constants C11 and C12 and the fabrication temperatures. In literature, the effects of fabrication temperatures on C11 and C12 needed to calculate thermal-induced stress σ₀ have been ignored. The new finding is that if the effects of fabrication temperatures on C11 and C12 are ignored, then, the values of stress σ₀ and σ will be overestimated and, then, not accurate. Another important finding is that the speed performance of nano pMOS transistors will increase if the fabrication temperature of silicon-germanium films used as stressors is increased.

To predict correctly the thermal-induced stress and speed performance of nano pMOS transistors, the effects of fabrication temperatures on the elastic constants required to calculate the thermal-induced intrinsic stress σ₀ should be taken into account.

There are three levels of originalities. The author considers the effects of the fabrication temperatures on extrinsic stress σ, intrinsic stress σ₀ and elastic constants C11 and C12.

The purpose of this paper is to provide a new three dimension physically based model to calculate the initial stress in silicon germanium (SiGe) film due to thermal mismatch after deposition. We should note that there are many other sources of initial stress in SiGe films or in the substrate. Here, the author is focussing only on how to model the initial stress arising from thermal mismatch in SiGe film. The author uses this initial stress to calculate numerically the resulting extrinsic stress distribution in a nanoscale PMOS transistor. This extrinsic stress is used by industrials and manufacturers as Intel or IBM to boost the performances of the nanoscale PMOS and NMOS transistors. It is now admitted that compressive stress enhances the mobility of holes and tensile stress enhances the mobility of electrons in the channel.

During thermal processing, thin film materials like polysilicon, silicon nitride, silicon dioxide, or SiGe expand or contract at different rates compared to the silicon substrate according to their thermal expansion coefficients. The author defines the thermal expansion coefficient as the rate of change of strain with respect to temperature.

Several numerical experiments have been used for different temperatures ranging from 30 to 1,000°C. These experiments did show that the temperature affects strongly the extrinsic stress in the channel of a 45 nm PMOS transistor. On the other hand, the author has compared the extrinsic stress due to lattice mismatch with the extrinsic stress due to thermal mismatch. The author found that these two types of stress have the same order (see the numerical results on Figures 4 and 12). And, these are great findings for semiconductor industry.

Front-end process induced extrinsic stress is used by manufacturers of nanoscale transistors as the new scaling vector for the 90 nm node technology and below. The extrinsic stress has the advantage of improving the performances of PMOSFETs and NMOSFETs transistors by enhancing mobility. This mobility enhancement fundamentally results from alteration of electronic band structure of silicon due to extrinsic stress. Then, the results are of great importance to manufacturers and industrials. The evidence is that these results show that the extrinsic stress in the channel depends also on the thermal mismatch between materials and not only on the material mismatch.

The model the author is proposing to calculate the initial stress due to thermal mismatch is novel and original. The author validated the values of the initial stress with those obtained by experiments in Al-Bayati et al. (2005). Using the uniaxial stress generation technique of Intel (see Figure 2). Al-Bayati et al. (2005) found experimentally that for 17 percent germanium concentration, a compressive initial stress of 1.4 GPa is generated inside the SiGe layer.

We first provide an overview of some predominant theoretical methods currently used for predicting thermal conductivity of thin dielectric films: the equation of radiative transfer, the temperature‐dependent thermal conductivity theories based on the Callaway model, and the molecular dynamics simulation. This overview also highlights temporal and spatial scale issues by looking at a unified theory that bridges physical issues presented in the Fourier and Cattaneo models. This newly developed unified theory is the so‐called C‐ and F‐processes constitutive model. This model introduces the notion of a new dimensionless heat conduction model number, which is the ratio of the thermal conductivity of the fast heat carrier F‐processes to the total thermal conductivity comprised of both the fast heat carriers F‐processes and the slow heat carriers C‐processes. Illustrative numerical examples for prediction of thermal conductivity in thin films are primarily presented.

The purpose of this paper is to provide a review of recent developments in nanoelectronic devices, with an emphasis on the materials and fabrication technologies employed.

This paper focuses on three critical fields of nanoelectronics: integrated circuits (ICs), sensors and displays. It describes recent developments and considers the materials and techniques used in their fabrication.

This paper shows that nanoelectronic developments, particularly experimental ICs, are progressing very rapidly but all manner of different materials and non‐standard fabrication processes are involved. Major efforts are underway to develop simple and cost‐effective techniques which will allow the high volume production of suitable nanomaterials and their incorporation into commercial nanoelectronic devices.

The paper provides an up‐to‐date review of nanoelectronic device developments and fabrication technologies.

The small dimensions of future device designs also imply a stronger effect of material boundary resistance. For nanoscale devices and structures, especially, interface phenomena often dominate their overall thermal behavior. The purpose of this paper is to propose molecular dynamics (MD) simulations to investigate the mechanical and thermal properties at Cu‐Al interface.

The two‐temperature model (TTM)‐MD model is used to describe the electron‐phonon scattering at interface of different metals. Before the simulation of heat transfer process, a non‐ideal Cu‐Al interface is constructed by simulating diffusion bonding.

According to the simulation results, in unsteady state, the temperature distribution and the displacements of atoms near the interface tend to generate stress and voids. It reveals the damage mechanics at the interface in heat transfer.

The atomic model proposed in this paper is computationally efficient for interfacial heat transfer problems, and could be used for investigation of other interfacial behaviors of dissimilar materials.

The purpose of this paper is to present an analytical drain current model for output characteristics of strained‐Si/SiGe bulk MOSFET.

A physics‐based model for current output characteristics and transconductance of strained‐Si/SiGe bulk devices has been developed incorporating the impact of strain (in terms of equivalent Ge mole fraction), strained silicon thin film thickness, gate work function, channel length and other device parameters. The accuracy of the results obtained using this model is verified by comparing them with 2D device simulations.

This model correctly predicts the output characteristics, I_DS−V_GS characteristics, transconductance and output conductance of the strained‐Si/SiGe MOSFET and demonstrates a significant enhancement in the drain current of the MOSFET with increasing strain in the strained‐Si thin film, i.e. with increasing equivalent Ge concentration in the SiGe bulk.

Can be implemented in a SPICE like simulator for studying circuit behaviour containing strained‐Si/SiGe bulk MOSFETs.

The model discussed in this paper can be easily implemented in a circuit simulator and used for the characterization of strained silicon devices. This complements the recent trend of investigation of new materials and device structures to maintain the rate of advancement in VLSI technology.

This paper presents, for the first time, a compact surface potential‐based analytical model for strained‐Si/SiGe MOSFETs which predicts the device characteristics reasonably well over their range of operation.

MAGNESIUM, because of its low density, has obvious possibilities as an aircraft structural material. The useful magnesium alloys have densities in the range 1·76 to 1·83, compared with the aluminium alloys range of about 2·5 to 2·8. The melting point of magnesium is 650 deg. C., almost identical with that of aluminium (660 deg. C.), so that generally the alloys of each of these base elements have applications in much the same temperature band.

THE element silicon (Si) has attained a dominant position in the field of manufacturing micro‐electronic components. This dominant position is due to properties which will perhaps assume even greater significance in the future. Silicon is universally applicable both for sensors, and for analogue and logic circuits as well as for memory cells. It is comparatively easy to work with. It is completely non‐toxic, and is therefore environmentally harmless. Supplies of silicon are almost limitless; after oxygen silicon is the second most common element in the earth's crust. Silicon crystallises in a diamond lattice (Fig. 1). Its universal applicability as a semiconductor is not synonymous with the optimal suitability for the current special application. The most far‐reaching proposal for overcoming the inadequacies of natural semiconductors came from L. Esaki. A superlattice structure (Fig. 2) is produced by arranging alternate layers of different elements. The atoms A and B are arranged periodically with a period length which superposes the natural period of the lattice. If the period of the superlattice is small (e.g. 3 to 100 atomic layers) new properties would be expected, which arise from the mixed crystals (synthetic semiconductor). The properties of the synthetic semiconductor are controllable by the geometrical dimensions and the concentrations of the superlattice structure.

THE month of exhibitions is upon us, and work study technicians will be interested in both the Mechanical Handling Exhibition at Earl's Court (May 9–19) and the Production Exhibition at Olympia (May 23–31). A preview of both these exhibitions is published on pages 28–56.