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The purpose of this paper is to focus on through‐silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented.

This design addresses the electronic packaging of 3D IC integration with a passive TSV interposer for high‐power, high‐performance, high pin‐count, ultra fine‐pitch, small real‐estate, and low‐cost applications. To achieve this, the design uses chip‐to‐chip interconnections through a passive TSV interposer in a 3D IC integration system‐in‐package (SiP) format with excellent thermal management.

A generic, low‐cost and thermal‐enhanced 3D IC integration SiP with a passive interposer has been proposed for high‐performance applications. Also, the origin of 3D integration and the overview and outlook of 3D Si integration and 3D IC integration have been presented and discussed. Some important results and recommendations are summarized: the TSV/redistribution layer (RDL)/integrated passive devices passive interposer, which supports the high‐power chips on top and low‐power chips at its bottom, is the gut and workhorse of the current 3D IC integration design; with the passive interposer, it is not necessary to “dig” holes on the active chips. In fact, try to avoid making TSVs in the active chips; the passive interposer provides flexible coupling for whatever chips are available and/or necessary, and enhances the functionality and possibly the routings (shorter); with the passive interposer, the TSV manufacturing cost is lower because the requirement of TSV manufacturing yield is too high (>99.99 percent) for the active chips to bear additional costs due to TSV manufacturing yield loss; with the passive interposer, wafer thinning and thin‐wafer handling costs (for the interposer) are lower because these are not needed for the active chips and thus adds no cost due to yield loss; with the current designs, all the chips are bare; the packaging cost for individual chips is eliminated; more than 90 percent of heat from the 3D IC integration SiP is dissipated from the backside of high‐power chips using a thermal interface material and heat spreader/sink; the appearance and footprint of current 3D IC integration SiP designs are very attractive to integrated device manufactures, original equipment manufactures, and electronics manufacturing services (EMS) because they are standard packages; and underfills between the copper‐filled TSV interposer and the high‐ and low‐power chips are recommended to reduce creep damage of the lead‐free microbump solder joints and prolong their lives.

The paper's findings will be very useful to the electronic industry.

The purpose of this paper is to provide a technical review of silicon micro‐electromechanical systems (MEMS) technology and its applications.

Following an introduction, the paper describes silicon MEMS fabrication and assembly techniques, considers a selection of commercially important products and their applications and concludes with a brief review of power MEMS research.

Silicon MEMS fabrication technology is derived from techniques used in semiconductor manufacture and has yielded a diverse and ever‐growing range of sensors, actuators and other miniaturised devices that find applications in a multitude of industries.

This paper provides a detailed technical review of MEMS technology and its applications.

One of the problems encountered by developers of inertial systems, such as gyroscopes and accelerometers, is the critical dependence of the eigenfrequencies of elastic suspensions (ES) on temperature when using substrates for sensors made of dielectric materials, such as borosilicate glass. The internal stresses arising in the ES caused by the difference in the temperature coefficients of linear expansion (TCLE) lead to deformation of the sensor and complication of the electronic part of the sensor. The purpose of this paper is to approach for in-plane and out-of-plane ES are considered that allow for minimization of the influence of internal stresses on eigenfrequencies.

Analytical, finite element and experimental results are considered. The temperature coefficient of thermal expansion, the Young’s modulus and the Poisson ratio are given as a function of temperature. The shape of the spring elements (SEs) and the construction of the elastic suspension are the main topics of focus in this study. The authors’ out-of-plane ES based on a meander-like spring element implemented via finite element modeling show good agreement with the experimental results.

Meander-like SEs have been developed that have lower temperature errors in comparison with traditional types of SEs. The main contribution to the change in the eigenfrequency from temperature is made by internal stresses that arose from the deformation of the bonded materials with different TCLE. The change of eigenfrequency from the temperatures that were calculated by finite element method did not exceed 0.15%, however, in practice, the scatter of the obtained characteristics for different samples showed a change of up to 0.3%.

This study shows a way to design and optimize the structure and theoretical background for the development of the microelectromechanical systems (MEMS) inertial module combining the functions of gyroscope and accelerometer. The obtained results will improve and expand the manufacturing technology of MEMS gyroscopes and accelerometers.

The purpose of this paper is to present a novel n‐buried‐PSOI sandwiched radio frequencies (RF) power lateral diffused metal‐oxide semiconductor (LDMOS) and analyze its output characteristics.

The small‐signal equivalent circuit for RF power LDMOS method is used to analyze the proposed structure and the simulation and optimization are done using the computer‐aided design tools.

This improved structure is clearly decreasing drain‐substrate parasitic capacitance. At 1 dB compression point, its output power, the power‐added efficiency and the breakdown voltage are higher than that of the conventional LDMOS.

This paper puts forward a novel n‐buried‐PSOI sandwiched structure of RF power LDMOS. The analysis indicates that the output characteristics of this device are a great improvement on the conventional LDMOS and the n‐buried‐PSOI, RF power LDMOS proposed by earlier authors.

This case is designed to achieve the following learning objectives: recognize the impact of personality traits on leadership style; identify the key elements in a turnaround strategy; examine leadership best practices from a gender perspective; and assess the role of strategic decision-making on company growth.

The case study describes how Lisa Su (Su), the first woman CEO of Advanced Micro Devices, helped turn around the debt-laden semiconductor firm within a decade through her transformational leadership, vision and values. The case first touches upon Su’s early life and education and the influence of her parents in shaping her personality. It then focuses on the first half of Su’s career, during which she was working on semiconductor projects and was involved in research and product development, and how she made the gradual shift to a people management role in her stint of over a decade at IBM followed by a leadership opportunity at Freescale Semiconductor Inc. The case then describes Su’s move to AMD in 2012 as Senior Vice President and General Manager of the company’s global business divisions at a time when AMD was nearly US$2.5bn in debt and revenues had increased only once in the previous five years. There were also rumors of bankruptcy and spin-offs after the company lost more than US$1bn in the year 2012. The cas

This case is meant for MBA students as part of their Organizational Behavior, Leadership, and Strategic Management curriculum.

Teaching notes Student feedback details.

CCS 11: Strategy.

This paper aims to provide a focused review on the geometrical designs for performance enhancement of piezoresistive microaccelerometers.

By analyzing working principle and conventional geometries, the improved research proposals are sorted into three groups in terms of their anticipated objectives, including sensitivity, resonant frequency and cross-axis sensitivity. Accessible methods are outlined and their merits and demerits are described.

Novel geometries obviously enhance the performance of accelerometers, and the efficacy can be further elevated by newer materials and fabrication processes.

This paper mainly focused on the improved geometrical designs for sensitivity, resonant frequency and cross-axis sensitivity. Other performance parameters or design schemes are not included in this paper.

This paper generalizes the available geometries and methods for the enhancement of sensitivity, resonant frequency and cross-axis sensitivity in piezoresistive accelerometers design.

The purpose of this paper is to present a novel n‐buried partial silicon‐on‐nothing (SON) structure of radio frequencies (RF) power lateral double‐diffused metal‐oxide‐semiconductor (LDMOS) and analyze its RF characteristics.

The small‐signal equivalent circuit for RF power LDMOS method is used to analyze the proposed structure and the simulation and optimization are done using 2D simulator MEDICI.

This improved structure is clearly decreasing drain‐substrate parasitic capacitance. At 1 dB compression point, its output power, the power‐added efficiency and the breakdown voltage is higher than that of the conventional LDMOS.

This paper usefully shows how SON having low‐dielectric constant can reduce the horizontal drain field and the drain‐substrate capacitance, and increase the breakdown voltage as a result.