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Digital Delta Sigma Modulator (DDSM) is used widely in electronic circuits including Radars, class-D power amplifiers and fractional frequency synthesizers. The purpose of this paper is to propose an implementation for MASH DDSMs named as Multi Modulus Reduced Complexity (MMRC) architecture.

This architecture will use a very simple pseudorandom Linear Feedback Shift Register (LFSR) dither signal with period N_d to randomize the digital MMRC modulator used for fractional frequency synthesizers. Using error masking methodology, the MMRC modulator can decrease the hardware consumption and increase accuracy of the fractional frequency synthesizer. Rules for selecting the appropriate word lengths of the constituent MMRC modulator are derived.

This paper contains three modulators. The first stage modulator is a variable modulus First Order Error Feedback Modulator and has a programmable modulus M1 that is not a power of two. The second and third stage modulators are the first order pseudorandom LFSR dithered MASH 1-1 and modified MASH 1-1-1, which have conventional modulo M2, M3, respectively. With optimum selection modulus M1, the new structure can synthesize the desired frequency exactly. Simulation results confirm the theoretical predictions. Also the results of circuit implementation proposed method reports 13 per cent reduction in hardware.

This paper for the first time proposes a nested sigma delta modulator with a pseudorandom shaped dither signal which reduced hardware complexity and increased the period of output signal. This modulator is exploited in the fractional frequency synthesizer to the output frequency can be set more accurately.

A third-order discrete time sigma delta modulator (SDM) is proposed with optimum performance by addressing instability and power dissipations issues, and a novel SDM architecture is designed and verified in behavioural modelling in MATLAB/SIMULINK environment. Simulation results show that performance parameters of proposed modulator achieved SNR of 105.41 dB, SNDR of 101.96 dB and DR of 17 bits for the signal bandwidth of 20 kHz.

This paper describes single-loop SDM design with optimum selection of integrator weights for physiological signal processing in IoT applications.

The proposed discrete time modulator designed with 1-bit quantizer and optimum oversampling ratio proved as power efficient. Integrator scaling coefficients are generated in LabVIEW environment for pure third-order noise shaping.

This paper contains the novelty in the work, and it is suitable for cognitive Internet of Things applications.

This paper attempted a novel approach for system-level modeling and simulation of sigma-delta modulator for low-frequency CMOS integrated analog to digital interfaces. Comparative analysis of various architectures topologies, circuit implementation techniques are described with analytical procedure for effective selection of topologies for targeted specifications.

Virtual instruments are presented in labview environment to analyze the correlation of circuit-level non-ideal effects with key design parameters over sampling ratio, coarse quantizer bits and loop filter order. A fourth-order single-loop sigma-delta modulator is designed and verified in MATLAB simulink environment with careful selection of integrator weights to meet stable desired performance.

The proposed designed achieved SNDR of 122 dB and 20 bit resolution satisfying high-resolution requirements of low-frequency biomedical signal processing applications. Even though the simulation performed at behavioral level, the results obtained are considered as accurate, by including all non-ideal and non-linear circuit errors in simulation process.

Virtual instruments using labview environment used to analyze the correlation of circuit-level non-ideal effects with key design parameters over sampling ratio, coarse quantizer bits and loop filter order for accurate design.

In actual application of a DC-DC boost converter, the input voltage and resistive load may be changed frequently, and these variations deteriorate the conventional controller performance. The purpose of this paper is to present an observer-based control scheme for a DC-DC boost converter with an unknown resistive load and input voltage.

To estimate the unknown input voltage and resistive load, a nonlinear observer is designed by using the Lyapunov stability theorem. In addition, the closed-loop stability of the proposed control scheme for the DC-DC boost converter is proven. To convert the continuous control input to discrete mode, a sigma–delta modulator is used.

The proposed control scheme is validated in different situations. The adaptive structure of the proposed control scheme is tested by the input voltage, load and reference signal variation, and the simulation results confirm the capability of the proposed observer-based control strategy.

The contribution of this paper is twofold: according to nonlinear controller design, the feedforward term of the nonlinear controller is obtained via the observer, and unlike the proportional–integral controller, performance deterioration in the input voltage and load variations are unraveled. The effectiveness of this method is validated by experimental implementation in the presence of load and input voltage variations, and the experimental results confirm the efficacy of the proposed strategy.

This paper aims to propose and demonstrate novel microphone sensors based on the frequency delta-sigma modulation (FDSM) technique, which replaces the conventional delta-sigma modulator in the delta-sigma analog-to digital converters. A key of the FDSM technology is to use a voltage-controlled oscillator (VCO) for converting an input analog signal to a 1-bit pulse-density modulated digital signal. High-performance sensors can be realized if the VCO is replaced by an oscillator whose oscillation frequency depends on an external physical parameter.

Microphone sensors are proposed based on FDSM that uses a suspended microstrip disk resonator, where the backside ground plane is replaced by a thin metal diaphragm. A resonant tunneling diode (RTD) oscillator is also used, as the performance of these sensors significantly depends on the oscillation frequency. To demonstrate the basic operation of the proposal, prototype devices were fabricated with an InGaAs/AlAs RTD.

A satisfactory noise shaping property, which is a significant nature of delta-sigma modulation, was demonstrated over three decades for the prototype device. A sound-sensing peak was also clearly observed when applying 1 kHz sound from a speaker.

High-performance ultrasonic microphone sensors can be realized if the sensors are fabricated by using a thin InP substrate with high-frequency oscillator design.

In this study, the authors proposed and experimentally demonstrated novel microphone sensors, which are promising as future ultrasonic sensors that have high dynamic range with wide bandwidth.

The purpose of this paper is to present analysis of the feedback predictive encoder-based analog-to-digital converter (ADC).

The use of feedback predictive encoder-based ADCs presents an alternative to the traditional two-stage pipeline ADC by replacing the input estimate producing first stage of the pipeline with a predictive loop that also produces an estimate of the input signal.

The overload condition for feedback predictive encoder ADCs is dependent on input signal amplitude and frequency, system gain and filter order. The limitation on the practical usable filter order is set by limit cycle oscillation. A boundary condition is defined for determination of maximum usable filter order. In a practical implementation of the predictive encoder ADC, the time allocated to the key functions of the gain stage and loop quantizer leads to optimization of the power consumption.

A practical switched capacitor implementation of the predictive encoder-based ADC is proposed. The power consumption of key circuit blocks is investigated.

This paper presents a methodology to optimize the bandwidth of predictive encoder ADCs. The overload and stability conditions may be used to determine the maximum input signal bandwidth for a given loop quantizer. Optimization of power consumption based on the allocation of time between the gain stage and the successive approximation register ADC operation is investigated. The lower bound of power consumption for this architecture is estimated.

As technology advances the demand for an analog-to digital converter has increased, as every application demands a converter as per its parameters. Currently, work is done on improvement of data converters at three levels of design – architectural, circuit and physical level. This paper aims to review the work done in the field of analog-to-digital converters (ADCs) at architectural and circuit level and discusses the achievements in this field. Furthermore, a new architecture is proposed, which works at higher resolution and provides optimum design parameters at low power consumption.

A hybrid architecture combining the features of synthetic approximation register and sigma-delta ADC is presented. The validity of the proposed design at architectural level is verified using MATLAB SIMULINK simulations.

The design simulation was tested for a sinusoidal wave of 1 V at the test frequency of 60 Hz. The design consumes least power, and is found to yield an error of the order less than 10–3 V, thus providing highly accurate digital output.

The design is applicable in many applications including biomedical systems, Internet-of-Things and earthquake engineering. This architecture can be further optimized to obtain better performance parameters.

Many important electronic systems are modelled by discrete‐time equations with nonlinearities that are discontinuous and piecewise‐linear, often arising as a result of quantization. Approximations based on linearization – the standard engineering response to nonlinearity – are often quite unhelpful in these systems, because of the form of the nonlinearity. Certain methods and results have been developed over a number of years for the analysis of discontinuous piecewise‐linear discrete‐time dynamics. The aim of this tutorial paper is to review that body of knowledge, and to show how it can be applied to representative electronic systems.

The paper uses an important electronic circuit – the ΣΔ modulator – as a central example, and considers the dynamical behaviour exhibited by this circuit and related circuits.

The circuits under investigation exhibit complex forms of behaviour that can be explained by the application of methods of nonlinear discrete‐time dynamics.

This paper is intended to provide a brief introduction to the body of research that exists into the behaviour of nonlinear discrete‐time circuits and systems with discontinuous piecewise‐linear nonlinearities.

To develop a wireless sensor micro‐systems containing all the components of data acquisition system, such as sensors, signal‐conditioning circuits, analog‐digital converter, embedded microcontroller unit (MCU), and RF communication modules. This has now become the focus of attention in many biomedical applications.

The system prototype consists of miniature FSK transceiver integrated with MCU in one small package, chip antenna, and capacitive interface circuitry based on Delta‐sigma modulator. At the base station side, an FSK receiver/transmitter is connected to another MCU unit, which send the received data or received instructions from a PC through a graphical user interface GUI. Industrial, scientific and medical band RF (433 MHz) was used to achieve half duplex communication between the two sides. A digital filtering has been used in the capacitive interface to reduce noise effects forming capacitance to digital converter. All the modules of the mixed signal system are integrated in a printed circuit board of size 22.46 × 20.168 mm.

An innovation circuits and system techniques for building advanced smart medical devices have been discussed. Low‐power consumption and high reliability are among the main criteria that must be given priority when designing such wirelessly powered microsystems. Switched capacitors readout circuits have been found to be suitable for pressure sensing low‐power applications.

The presented wireless prototype needs a second phase of development that will lead to a further reduction in both size and power consumption. Currently, the main limitation of the RF system is the number of working hours according to the selected battery.

The developed system was found to be useful in terms of measuring pressure and temperature in a system of either slow or fast physical change. It would be a good idea to explore the system performance in human or animal trials.

This paper fulfils useful information for capacitive interface circuitries and presents a new short‐range wireless system that has different design features.