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Article
Publication date: 15 July 2022

Muhammad Yasir Faheem, Muhammad Basit Azeem, Abid Ali Minhas, Shun'an Zhong and Xinghua Wang

RF transceiver module is considered a vital part of any wireless communication system. This module consists of two important parts the RF transceiver and analog-to-digital…

Abstract

Purpose

RF transceiver module is considered a vital part of any wireless communication system. This module consists of two important parts the RF transceiver and analog-to-digital converter (ADC). Usually, both these parts – RF transceiver and ADC – are used to enhance the perspective of size and power. The data processing in 4G communication makes hurdles and need research attention to make it faster and smaller in size. Accuracy and fast processing are the critical challenges in the modern communication system.

Design/methodology/approach

After theoretical and practical investigations, this research work proposes key new techniques for the RF transceiver module. These techniques will make RF transceiver small, power-efficient and on the other hand, make dual SAR-ADC more effective as well. The proposed design has no intermediate frequency where the RF transceiver is reduced its major blocks from five to four, which includes crystal oscillator, phase lock loop, power amplifier and low noise amplifier. Moreover, the shared circuitry is introduced in the architecture of the SAR-ADC for the production of dual outputs, specifically in bootstrapped switch and comparator.

Findings

The miniaturized RF transceiver and SAR-ADC are well tested separately before the plantation on the printed circuit board (PCB). The operating voltage and frequency of the RF transceiver module are 1.2 V and 5.8 GHz, where the sampling rate, bandwidth and output power are 25 MHz, 200 MHz and 5 dBm, respectively. The core area of the PCB is 58.13 mm2. The bandwidth efficiency is 93% using surface acoustic wave less transmitter. The circuit is based on the library of 90 nm CMOS technology.

Originality/value

The entire circuit is highly synchronized with the input and reference clocks to avoid self-interference.

Details

Microelectronics International, vol. 39 no. 4
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 3 February 2020

Muhammad Yasir Faheem, Shun'an Zhong, Xinghua Wang and Muhammad Basit Azeem

Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient…

Abstract

Purpose

Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC.

Design/methodology/approach

A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration.

Findings

The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms.

Originality/value

The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

Article
Publication date: 8 March 2021

Muhammad Yasir Faheem, Shun'an Zhong, Xinghua Wang and Muhammad Basit Azeem

There are many types of the ADCs implemented in the mobile and wireless devices. Most of these devices are battery operated and operational at low input voltage. SAR ADC is…

Abstract

Purpose

There are many types of the ADCs implemented in the mobile and wireless devices. Most of these devices are battery operated and operational at low input voltage. SAR ADC is popular for its low power operations and simple architecture. Scientists are still working to make its working faster under the same low power area. There are many SAR-ADC implemented in the past two decades, but still, there is a big room for dual SAR-ADC.

Design/methodology/approach

The authors are presenting a dual SAR-ADC with a smaller number of components and blocks. The proposed ultra-low-power circuit of the SAR-ADC consists of four major blocks, which include Bee-bootstrap, Spider-Latch dual comparator, dual SAR-logic and dual digital to analog converter. The authors have used the 90-nm CMOS library for the construction of the design.

Findings

The power breaks down of the comparator are dramatically improved from 0.006 to 0.003 uW. The ultimate design has 5 MHz operating frequency with 25 KS/s sampling frequency. The supply voltage is 1.2 V with 35.724 uW power consumption. Signal-to-noise and distortion ratio and spurious-free dynamic range are 65 and 84 dB, respectively. The Walden's figure of merits calculated 7.08 fj/step.

Originality/value

The authors are proposing two-in-one circuit for SAR-ADC named as “dual SAR-ADC”, which obeys the basic equation of duality, derived and proved under the heading of proposed solution. It shows a clear difference between the performance of two circuit-based ADC and one dual circuit ADC. The number of components is reduced by sharing the work load of some key components.

Article
Publication date: 1 December 2021

Muhammad Yasir Faheem, Shun'an Zhong, Muhammad Basit Azeem and Xinghua Wang

Successive Approximation Register-Analog to Digital Converter (SAR-ADC) has been achieved notable technological advancement since the past couple of decades. However, it’s not…

Abstract

Purpose

Successive Approximation Register-Analog to Digital Converter (SAR-ADC) has been achieved notable technological advancement since the past couple of decades. However, it’s not accurate in terms of size, energy, and time consumption. Many projects proposed to make it energy efficient and time-efficient. Such designs are unable to deliver two parallel outputs.

Design/methodology/approach

To this end, this study introduced an ultra-low-power circuitry for the two blocks (bootstrap and comparator) of 11-bit SAR-ADC. The bootstrap has three sub-parts: back-bone, left-wing and right-wing, named as bat-bootstrap. The comparator block has a circuitry of the two comparators and an amplifier, named as comp-lifier. In a bat-bootstrap, the authors plant two capacitors in the back-bone block to avoid the patristic capacitance. The switching system of the proposed design highly synchronized with the short pulses of the clocks for high accuracy. This study simulates the proposed circuits using a built-in Cadence 90 nm Complementary Metal Oxide Semiconductor library.

Findings

The results suggested that the response time of two bat-bootstrap wings and comp-lifier are 80 ns, 120 ns, and 90 ns, respectively. The supply voltage is 0.7 V, wherever the power consumption of bat-bootstrap, comp-lifier and SAR-ADC are 0.3561µW, 0.257µW and 35.76µW, respectively. Signal to Noise and Distortion Ratio is 65 dB with 5 MHz frequency and 25 KS/s sampling rate. The input referred noise of the amplifier and two comparators are 98µVrms, 224µVrms and 224µVrms, respectively.

Originality/value

Two basic circuit blocks for SAR-ADC are introduced, which fulfill the duality approach and delivered two outputs with highly synchronized clock pulses. The circuit sharing concept introduced for the high performance SAR-ADCs.

Article
Publication date: 10 November 2020

Weiling Tuo, Shun'an Cao and Jie Zhong

The purpose of this study was to investigate the corrosion of low molecular organic acids from water-steam cycles such as acetic acid and formic acid in mental parts of steam…

Abstract

Purpose

The purpose of this study was to investigate the corrosion of low molecular organic acids from water-steam cycles such as acetic acid and formic acid in mental parts of steam turbine initial condensation zone.

Design/methodology/approach

The corrosion behavior of gray cast iron in initial condensate containing different concentrations of acetic acid and formic acid was studied by weight loss test, scanning electron microscopy, energy dispersive spectroscopy and X-ray diffraction.

Findings

The results indicated that gray cast iron had a certain degree of corrosion in the simulated initial condensate containing acetic acid and formic acid, but the acid corrosion of gray cast iron was not only caused by low molecular organic acid but also affected by inorganic anions such as Cl. When Cl existed, after removing corrosion products, surface analysis results proved that the surface of gray cast iron was rough and uneven with many cracks, which was corrected more serious.

Originality/value

The corrosion behavior of thermal equipment by low molecular organic acids and inorganic anions in water-steam cycles was studied. The research results can provide theoretical guidelines for corrosion control of steam turbine in power plants.

Details

Anti-Corrosion Methods and Materials, vol. 67 no. 6
Type: Research Article
ISSN: 0003-5599

Keywords

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