Search results

Whatever one may feel is the importance of particular interconnection and assembly technologies with which one is associated, Thin Film or Thick Film Hybrid, PCB Through Hole, Surface Mounting, etc., the driving force in electronics is the high degree of low cost functionality brought by semiconductor technology. However, semiconductor science cannot provide systems solutions on its own and needs to be combined with suitable interconnection and assembly technologies to bring its potential processing power to fulfilment. Hybrid technology holds a key role in the use of silicon in overall system integration. On hybrid substrates semiconductors can be applied in any of the forms available, from bare dice to encapsulated, tested and burnt‐in complex functions in LSI. Over the years hybrids have developed, needing semiconductors as the active elements in providing functional modules. The relationship between the technologies has been close but not always in perfect harmony at the commercial interfaces. The first part of this paper reviews development of semiconductors in relation to the forms of packaging available for application in hybrid assembly including the emergent means being adopted to tackle the problems of ever increasing lead counts that will be with us for some time until the dream of total self‐sufficiency on silicon becomes a reality. The second part of the paper reviews silicon design options with the emphasis on the relevance of combining silicon implementation with hybrid methods.

Self‐consistent electrothermal simulation of modern semiconductor devices is required for the accurate and efficient design and optimization of many semiconductor devices. The need to perform this type analysis in order to predict the behavior of power devices was realized many years ago. It is now clear that nonisothermal analysis can be very important for VLSI devices as well.

A mathematical analysis of the time‐dependent multi‐dimensional Hydrodynamic model is performed to determine the well‐posed boundary conditions for semiconductor device simulation. The number of independent boundary conditions that need to be specified at electrical contacts of a semi‐conductor device are derived. Using the classical energy method, a mathematical relation among the physical parameters is established to define the well‐posed boundary conditions for the problem. Several possible sets of boundary conditions are given to illustrate the proper boundary conditions. Natural boundary conditions that can be specified are obtained from the boundary integrals of the weak‐form finite element formulations. An example is included to illustrate the importance of well‐posedness of the boundary conditions for device simulation.

To present a new direct solution method for the Boltzmann‐Poisson system for simulating one‐dimensional semiconductor devices.

A combination of finite difference and finite element methods is applied to deal with the differential operators in the Boltzmann transport equation. By taking advantage of a piecewise polynomial approximation of the electron distribution function, the collision operator can be treated without further simplifications. The finite difference method is formulated as a third order WENO approach for non‐uniform grids.

Comparisons with other methods for a well‐investigated test case reveal that the new method allows faster simulations of devices without losing physical information. It is shown that the presented model provides a better convergence behaviour with respect to the applied grid size than the Minmod scheme of the same order.

The presented direct solution methods provide an easily extensible base for other simulations in 1D or 2D. By modifying the boundary conditions, the simulation of metal‐semiconductor junctions becomes possible. By applying a dimension by dimension approximation models for two‐dimensional devices can be obtained.

The new model is an efficient tool to acquire transport coefficients or current‐voltage characteristics of 1D semiconductor devices due to short computation times.

New grounds have been broken by directly solving the Boltzmann equation based on a combination of finite difference and finite elements methods. This approach allows us to equip the model with the advantages of both methods. The finite element method assures macroscopic balance equations, while the WENO approximation is well‐suited to deal with steep gradients due to the doping profiles. Consequently, the presented model is a good choice for the fast and accurate simulation of one‐dimensional semiconductor devices.

A program for numerical simulation of two‐dimensional semiconductor devices coupled with an external circuit is described. The circuit equations are formulated using modified nodal analysis to allow an arbitrary configuration of elements like, e.g., also semiconductor compact models. Coupling to the numerical devices is attained via their admittance matrix leading to a two‐level Newton method. To calculate this matrix two methods are compared: (a) a linearization scheme and (b) a secant method. The comparison shows a significant speed advantage of the secant method despite its lower rate of convergence. The linearization scheme, however, is the more stable and robust method and should be used in critical cases where convergence problems can occur. An efficient bypassing scheme was developed for the linearization scheme leading to a computation speed comparable to that of the secant method, but maintaining the better convergence properties. A further advantage of the two‐level Newton method used in this work is that the CPU‐time consuming solution for the numerical devices can be done in parallel on different processors. Several examples are given to demonstrate the capabilities of the developed simulator.

This paper aims to present an analysis of a hybrid high‐voltage switch based on the parallel connection of IGBT and IGCT. The proposed configuration combines the advantages of both semiconductors, resulting in substantially reduced power losses. Such energy efficient switches could be used in high‐power systems where the requirements of high switching frequency or decreased cooling systems are a major concern.

The operation principle of the switch is described and simulated. The power dissipation is estimated at different operation conditions. Further, the implementation possibilities of the proposed switch configuration in a three‐level NPC inverter are analysed. The operation with the proposed PWM control algorithm is simulated and inverter power loss distribution is estimated.

According to estimations, the proposed hybrid switch configuration allows the reduction of total losses in semiconductors by at least 50 percent. If two of these switches are used in a three‐level NPC inverter as outer switches, the total losses of the inverter are reduced by 27 percent, at the same time the losses in the most stressed semiconductor device are reduced by a factor of 2.25. Therefore, achieving higher power density is possible.

The proposed switch configuration is intended for high‐power (>500 KVA) industrial, marine and railway traction systems, such as FACTS and high power variable frequency AC drives.

The paper presents the novel energy‐efficient high‐voltage switch based on the parallel connection of commercially available IGBTs and IGCTs.

Time and frequency domain complementary numerical models of microwave non‐linear circuits using two‐terminal active semiconductor devices are presented. Their main feature is the use of numerical one‐dimensional macroscopic physical models as semiconductor device models. Their respective capability is illustrated by some results of a study devoted to the optimization of millimeter‐wave avalanche diode frequency multipliers.

The purpose of this paper is to deal with the self-heating of semiconductor nano-devices.

Transport in silicon semiconductor devices can be described using the Drift-Diffusion model, and Direct Simulation Monte Carlo (MC) of the Boltzmann Transport Equation.

A new estimator of the heat generation rate to be used in MC simulations has been found.

The new estimator for the heat generation rate has better approximation properties due to reduced statistical fluctuations.

This paper presents a computer‐aided design (CAD) tool for the design of isolated dc‐dc converters.

This tool, developed in Matlab environment, is based on multiobjective optimization (MO) using genetic algorithms. The Elitist Nondominated Sorting Genetic Algorithm is used to perform search and optimization whereas analytical models are used to model the power converters. The design problem requires minimizing the weight, losses and cost of the converter while ensuring the satisfaction of a number of constraints. The optimization variables are, as for them, the operating frequency, the current density, the maximum flux density, the transformer dimensions, the wire diameter, the core material, the conductor material, the converter topology (among Flyback, Forward, Push‐Pull, half‐bridge and full‐bridge topologies), the number of semiconductor devices associated in parallel, the number of cells associated in series or parallel as well as the kinds of input and output connections (serial or parallel) of these cells. Finally, the design of an auxiliary railway power supply is presented and discussed.

The results show that such tool to design dc‐dc power converters presents several advantages. In particular, it proposes to the designer a set of solutions – instead of a single one – so that he can choose a posteriori which solution best fits the application under consideration. Moreover, interesting solutions not considered a priori can be found with this tool.

To the best of the authors’ knowledge, such a CAD tool including a MO procedure taking several topologies into account has not been suggested so far.

Numerical device simulation is developed to study the steady‐state and transient current‐voltage characteristics of double heterostructure AlGaAs/GaAs PNPN electro‐photonic device when its performance is influenced by the presence of interface and bulk recombination mechanism. The simulation results show that the holding current and voltage and the breakover point are strongly affected by varying the minority carrier lifetime at outer heterojunctions. Numerical results also indicate that shortening the minority carrier lifetime in the inner PN homojunction region only increases the OFF‐state current. These results are in agreement with experimental data on AlGaAs/GaAs PNPN devices. The numerical modelling approach taken in this study is shown to be essential in the design and optimization of PNPN switch.