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A real-time production scheduling method for semiconductor back-end manufacturing process becomes increasingly important in industry 4.0. Semiconductor back-end manufacturing process is always accompanied by order splitting and merging; besides, in each stage of the process, there are always multiple machine groups that have different production capabilities and capacities. This paper studies a multi-agent based scheduling architecture for the radio frequency identification (RFID)-enabled semiconductor back-end shopfloor, which integrates not only manufacturing resources but also human factors.

The architecture includes a task management (TM) agent, a staff instruction (SI) agent, a task scheduling (TS) agent, an information management center (IMC), machine group (MG) agent and a production monitoring (PM) agent. Then, based on the architecture, the authors developed a scheduling method consisting of capability & capacity planning and machine configuration modules in the TS agent.

The authors used greedy policy to assign each order to the appropriate machine groups based on the real-time utilization ration of each MG in the capability & capacity (C&C) planning module, and used a partial swarm optimization (PSO) algorithm to schedule each splitting job to the identified machine based on the C&C planning results. At last, we conducted a case study to demonstrate the proposed multi-agent based real-time production scheduling models and methods.

This paper proposes a multi-agent based real-time scheduling framework for semiconductor back-end industry. A C&C planning and a machine configuration algorithm are developed, respectively. The paper provides a feasible solution for semiconductor back-end manufacturing process to realize real-time scheduling.

This study aims to examine the impacts of higher memory dependencies on a novel semiconductor material that exhibits generalized photo-piezo-thermo-elastic properties. Specifically, the research focuses on analyzing the behavior of the semiconductor under three distinct temperature models.

The study assumes a homogeneous and orthotropic piezo-semiconductor medium during photo-thermal excitation. The field equations have been devised to encompass higher order parameters, temporal delays and a specifically tailored kernel function to address the problem. The eigenmode technique is used to solve these equations and derive analytical expressions.

The research presents graphical representations of the physical field distribution across different temperatures, higher order plasma heat conduction models and time. The results reveal that the amplitude of the distribution profile is markedly affected by factors such as the memory effect, time, conductive temperature and spatial coordinates. These factors cannot be overlooked in the analysis and design of the semiconductor.

Specific cases are also discussed in detail, offering the potential to advance the creation of precise models and facilitate future simulations.

The research offers valuable information on the physical field distribution across various temperatures, allowing engineers and designers to optimize the design of semiconductor devices. Understanding the impact of memory effect, time, conductive temperature and spatial coordinates enables device performance and efficiency improvement.

This manuscript is the result of the joint efforts of the authors, who independently initiated and contributed equally to this study.

This book chapter focuses on firstly social innovation and tools used to address the social needs and foster social innovation initiatives. Looking at the world economic forum and how it supports the social innovations, currency swings, low paying jobs growing rapidly, rapid change and growth as a result of high volatility and high returns, respectively. Secondly looking at the emerging market brought about by the social innovations and how they interconnect. Leading innovation emerging market has three main industries semiconductors, fin-tech, and electric cars. It also looks at the significance of technology in the development of business emerging markets, the role of technology in the emerging market and activities over the decades. Small firms in emerging areas face three major challenges which technology might help overcome. The challenges are trust, sustainability, and network. The role of technology replacing analog chip used for power supply, sensors, wideband signal make up the large semiconductors in the United States replaced with digital chip such as logical operations, data storage, computer information management all this have given birth to artificial intelligence, autonomous machines, self-driving cars, supply-chain management, cloud computing, and software-as-a-service (SaaS) applications are all made possible by digital chips. These are also used for e-commerce, mobile payment, fine-tech, 5G telecom, health-care advancement, remote learning, online entertainment, and cloud computing. Technical advancements that has sparked a revolution that would be especially advantageous for emerging market and small-cap enterprises are the causes of these benefits of how it has affected countries such as Europe, the United States, China, and India to mention a few.

In this paper, we evaluated the impact of the US “Chip Act” on the participation of the Chinese electronics industry in the global value chain based on the dynamic CGE model. This is a meaningful attempt to use the GTAP-VA model to analyze the electronics industry in China.

We employ a Dynamic GTAP-VA Model to quantitatively evaluate the economic repercussions of the “Chip Act” on the Chinese electronic industries' GVC participation from 2023 to 2040.

The findings depict a discernible contraction in China’s electronic sector by 2040, marked by a −2.95% change in output, a −3.50% alteration in exports and a 0.45% increment in imports. Concurrently, the U.S., EU and certain Asian economies exhibit expansions within the electronic sector, indicating a GVC realignment. The “Chip Act” implementation precipitates a significant divergence in GVC participation across different countries and industries, notably impacting the electronics sector.

Through a meticulous temporal analysis, this manuscript unveils the nuanced economic shifts within the GVC, substantially bridging the empirical void in existing literature. This narrative accentuates the profound implications of policy regulations on global trade dynamics, contributing to the discourse on international economic policy and industry evolution.

We evaluated the impact of the US “Chip Act” on the participation of the Chinese electronics industry in the global value chain based on the dynamic CGE model. This is a meaningful attempt to use the GTAP-VA model to analyze the electronics industry in China.

The interaction between policy regulations and global value chain (GVC) dynamics is pivotal in understanding the contemporary global trade framework, especially within technology-driven sectors. The US “Chips Act” represents a significant regulatory milestone with potential ramifications on the Chinese electronic industries' engagement in the GVC.

The significance of this paper is that it quantifies for the first time the impact of the US Chip Act on the GVC participation index of East Asian countries in the context of US-China decoupling. With careful consideration of strategic aspects, this paper substantially fills the empirical gap in the existing literature by presenting subtle economic changes within GVCs, highlighting the profound implications of policy regulation on global trade dynamics.

The purpose of this paper is to design a cascaded Multilevel inverter with reduce number of switches for high power applications. This paper came up with an innovative three-phase multilevel inverter (MLI) topology, which is a cascaded structure based on classical three-legged voltage source inverter (VSI) bridges as an individual module. The prominent advantage of this topology is that it requires only one direct current (DC) link system. The main characteristic of it is that a higher number of voltage levels can be achieved with considerably a smaller number of semiconductor switches, which improves the reliability, power quality, cost and size of the system significantly.

The individual modules are cascaded through three-phase transformers to provide higher voltage at the output with the higher number of voltage levels. In this work, the phase-shifted pulse width modulation technique is implemented to verify the result.

The proposed topology is compared with three-phase cascaded H-bridge MLI (CHB-MLI) and a modified CHB-MLI topology and found better in many aspects. The proposed MLI can produce a higher number of voltage levels with fewer semiconductor switches and associated triggering circuitry. As the device count in the proposed MLI is less compared to other MLI discussed, it tends to have less switching and conduction loss which increases the efficiency and reliability. As the number of level increases, the voltage profile and the total harmonic distortion of the proposed MLI improves.

This is a transformer-based modular cascaded MLI, which is based on classical VSI bridges. Here in this topology, a single module provides all three phases. So, a single string of cascaded modules is enough for three-phase multilevel voltage generation.