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The conventional design method relies on a priori knowledge, which limits the rapid and efficient development of electronic packaging structures. The purpose of this study is to propose a hybrid method of data-driven inverse design, which couples adaptive surrogate model technology with optimization algorithm to to enable an efficient and accurate inverse design of electronic packaging structures.

The multisurrogate accumulative local error-based ensemble forward prediction model is proposed to predict the performance properties of the packaging structure. As the forward prediction model is adaptive, it can identify respond to sensitive regions of design space and sample more design points in those regions, getting the trade-off between accuracy and computation resources. In addition, the forward prediction model uses the average ensemble method to mitigate the accuracy degradation caused by poor individual surrogate performance. The Particle Swarm Optimization algorithm is then coupled with the forward prediction model for the inverse design of the electronic packaging structure.

Benchmark testing demonstrated the superior approximate performance of the proposed ensemble model. Two engineering cases have shown that using the proposed method for inverse design has significant computational savings while ensuring design accuracy. In addition, the proposed method is capable of outputting multiple structure parameters according to the expected performance and can design the packaging structure based on its extreme performance.

Because of its data-driven nature, the inverse design method proposed also has potential applications in other scientific fields related to optimization and inverse design.

This study aims to simulate molded printed circuit board (PCB) warpage behavior under reflow temperature distribution. Simulation models are used to estimate dynamic warpage behavior for different form factor sizes.

This study analyzes warpage during the reflow process. The shadow moiré experiment methodology is used to collect data on the dynamic warpage performance of a model with a form factor of 10mm × 10mm × 1mm. The temperature profile with heating from 25°C to 300°C at intervals of 50°C is used, and the sample is made to undergo a cooling process until it reaches the room temperature. Subsequently, ANSYS static structural simulation is performed on similar form factor models to ascertain the accuracy of the simulation results.

Results show that the deformation and total force induced by coefficient of thermal expansion (CTE) mismatch are examined based on the warpage performance of models with different sizes, that is, 45mm × 45mm × 1mm and 45mm × 15mm × 1mm. Compared with the experimental data, the simulated modeling accuracy yields a less than 5% deviation in the dynamic warpage prediction at a reflow temperature of 300°C. Results also reveal that the larger the model, the larger the warpage changes under the reflow temperature.

The simulated warpage is limited to the temperature and force induced by CTE mismatch between two materials. The form factor of the ball-grid array model is limited to only three different sizes. The model is assumed to be steady, isothermal and static. The simulation adopts homogenous materials, as it cannot accurately model nonhomogeneous multilayered composite materials.

This study can provide engineers and researchers with a profound understanding of molded PCB warpage, minimal resource utilization and the improved product development process.

The accurate prediction of molded PCB warpage can enable efficient product development and reduce resources and production time, thereby creating a sustainable environment.

The literature review points out that warpage in various types of PCBs was successfully examined, and that considerable efforts were exerted to investigate warpage reduction in PCB modules. However, PCB warpage studies are limited to bare PCBs. To the best of the authors’ knowledge, the examination of warpage in a molded PCB designed with a molded compound cover, as depicted in Figure 3, is yet to be conducted. A molded compound provides strong lattice support for PCBs to prevent deformation during the reflow process, which is a topic of considerable interest and should be explored.

This paper aims to investigate the effect of physical vapor deposition (PVD)-coated stencil wall aperture on the life span of fine-pitch stencil printing.

The fine-pitch stencil used in this work is fabricated by electroform process and subsequently nano-coated using the PVD process. Stencil printing process was then performed to print the solder paste onto the printed circuit board (PCB) pad. The solder paste release was observed by solder paste inspection (SPI) and analyzed qualitatively and quantitatively. The printing cycle of up to 80,000 cycles was used to investigate the life span of stencil printing.

The finding shows that the performance of stencil printing in terms of solder printing quality is highly dependent on the surface roughness of the stencil aperture. PVD-coated stencil aperture can prolong the life span of stencil printing with an acceptable performance rate of about 60%.

Stencil printing is one of the important processes in surface mount technology to apply solder paste on the PCB. The stencil’s life span greatly depends on the type of solder paste, stencil printing cycles involved and stencil conditions such as the shape of the aperture, size and thickness of the stencil. This study will provide valuable insight into the relationship between the coated stencil wall aperture via PVD process on the life span of fine-pitch stencil printing.

The purpose of this paper is to illustrate the new technical demands and reliability challenges to printed circuit board (PCB) designs, materials and processes when the transmission frequency increases from Sub-6 GHz in previous generations to millimeter (mm) wave in fifth-generation (5G) communication technology.

The approach involves theoretical analysis and actual case study by various characterization techniques, such as a stereo microscope, metallographic microscope, scanning electron microscope, energy dispersive spectroscopy, focused ion beam, high-frequency structure simulator, stripline resonator and mechanical test.

To meet PCB signal integrity demands in mm-wave frequency bands, the improving proposals on copper profile, resin system, reinforcement fabric, filler, electromagnetic interference-reducing design, transmission line as well as via layout, surface treatment, drilling, desmear, laminating and electroplating were discussed. And the failure causes and effects of typical reliability issues, including complex permittivity fluctuation at different frequencies or environments, weakening of peel strength, conductive anodic filament, crack on microvias, the effect of solder joint void on signal transmission performance and soldering anomalies at ball grid array location on high-speed PCBs, were demonstrated.

The PCB reliability problem is the leading factor to cause failures of PCB assemblies concluded from statistical results on the failure cases sent to our laboratory. The PCB reliability level is very essential to guarantee the reliability of the entire equipment. In this paper, the summarized technical demands and reliability issues that are rarely reported in existing articles were discussed systematically with new perspectives, which will be very critical to identify potential reliability risks for PCB in 5G mm-wave applications and implement targeted improvements.

This paper aims to improve the life of the printed circuit boards (PCB) used in computers based on modal analysis by increasing the natural frequency of the PCB assembly.

In this work, through experiments and numerical simulations, an attempt has been made to increase the fundamental natural frequency of the PCB assembly as high as practically achievable so as to minimize the impacts of dynamic loads acting on it. An optimization tool in the finite element software (ANSYS) was used to search the specified design space for the optimal support location of the six fastening screws.

It is observed that by changing the support locations based on the optimization results the fundamental natural frequency can be raised up to 51.1% and the same is validated experimentally.

Manufacturers of PCBs used in computers fix the support locations based on symmetric feature of the board not on the dynamic behavior of the assembly. This work might lead manufacturers to redesign the location of other surface mount components.

This work provides guidelines for PCB manufacturers to finalize their support locating points which will improve the dynamic characteristics of the PCB assembly during its functioning.

This study provides a novel method to improve the life of PCB based on support locations optimization which includes majority of the surface mount components that contributes to the total mass the PCB assembly.

This paper aims to summarise the effects of ZnO nanoparticles (0.1, 0.3, 0.5, 0.7 and 1.0 Wt.%) on the structure, mechanical, electrical and thermal stability of Sn–3.5Ag–0.5Cu (SAC355) solder alloys for high-performance applications.

The phase identification and morphology of the solders were studied using X-ray diffraction and scanning electron microscopy. Thermal parameters were investigated using differential scanning calorimetry. The elastic parameters such as Young's modulus (E) and internal friction (Q⁻¹) were investigated using the dynamic resonance technique, whereas the Vickers hardness (Hv) and creep indentation (n) were examined using a Vickers microhardness tester.

Microstructural analysis revealed that ZnO nanoparticles (NPs) were distributed uniformly throughout the Sn matrix. Furthermore, addition of 0.1, 0.3 and 0.7 Wt.% of ZnO NPs to the eutectic (SAC355) prevented crystallite size reduction, which increased the strength of the solder alloy. Mechanical parameters such as Young's modulus improved significantly at 0.1, 0.3 and 0.7 Wt.% ZnO NP contents compared to the ZnO-free alloy. This variation can be understood by considering the plastic deformation. The Vickers hardness value (Hv) increased to its maximum as the ZnO NP content increased to 0.5. A stress exponent value (n) of approximately two in most composite solder alloys suggested that grain boundary sliding was the dominant mechanism in this system. The electrical resistance (ρ) increased its maximum value at 0.5 Wt.% ZnO NPs content. The addition of ZnO NPs to plain (SAC355) solder alloys increased the melting temperature (T_m) by a few degrees.

Development of eutectic (SAC355) lead-free solder doped with ZnO NPs use for electronic packaging.