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Aims to explain the main requirements for printed circuit boards (PCBs) and to determine the survival rate of boards in lead‐free assembly.

The first two main requirements are the survival of 5‐6 cycles lead free reflow with peak temperatures of up to 260°C and an identical or even better board reliability of such boards compared to todays eutectic soldered ones. In a first series of tests the influence of base materials, reflow temperature gradient and peak temperature on PCB survival rate are investigated. Thermo‐mechanical data of different epoxy‐based materials are compared to survival rate investigations using repeated reflow tests. The impact of PCB manufacturing and design on the lead free performance is discussed. A second series of investigations is air‐to‐air life cycle tests of daisy chain boards out of different epoxy‐based materials with varying preconditioning were done.

The tests showed that dicy cured epoxy base materials are not able to withstand the thermal stress of the mentioned soldering steps. Board design and the heating gradient in reflow also influence the assembly performance. Thermal cycling tests (air‐to‐air), showed clearly the effect of reflow temperature and number of reflow cycles on through‐hole reliability. There was no significant impact of z‐axis‐expansion on the through‐hole failure rate in air‐to‐air cycling.

Provides further information on the lead‐free assembly of PCBs.

This paper discusses chip removal and replacement processes of flip chip assemblies (FCAs) on printed wiring boards (PWBs). The original chip connection is achieved via mass reflow as in a surface mount assembly process. The FCA interconnection is one involving a surrogate solder bump on a chip and a lower melt solder on the PWB pads that fuses with the bump during reflow. The chip removal process thus entails melting the lower melt solder locally using hot gas. The following considerations will be discussed in the paper: chip size, chip removal methodology, local vs mass reflow for replacement attachment, solder height, the impact of multiple reflows on the solder joint integrity of assemblies. The use of the flip chip rework machine to remove ball grid arrays (BGAs) and quad flatpacks (QFPs) will be briefly addressed.

The purpose of this paper is to report the effect of multiple reflow cycles on ball impact test (BIT) responses and fractographies obtained at an impact velocity of 500 mm/s on Sn‐4Ag‐0.5Cu solder joints.

Solder balls were mounted on copper substrate pads with immersion tin surface finish, supplied by two vendors. For these particular test vehicles and test conditions, fracture near the interface between the interfacial Cu₆Sn₅ intermetallic compound (IMC) and copper pad was identified as the only failure mode induced by BIT.

Measurement results indicate that BIT characteristics in general degrade as the number of reflow cycles increases. Furthermore, scanning electron microscopy observations show that the thickness and grain size of interfacial Cu₆Sn₅ increase with increasing number of reflow cycles. This correlation confirms the familiar notion that a thicker Cu₆Sn₅ degrades the interfacial strength.

There are few reports that can attribute failure directly to the IMC(s) at the interface. This paper, however, successfully correlates the weakening solder joints with the thickening and shape changes of IMC(s) in a direct way.

This study aims to investigate the thermal fracture mechanism of moisture-preconditioned SAC305 ball grid array (BGA) solder joints subjected to multiple reflow and thermal cycling.

The BGA package samples are subjected to JEDEC Level 1 accelerated moisture treatment (85 °C/85%RH/168 h) with five times reflow at 270 °C. This is followed by multiple thermal cycling from 0 °C to 100 °C for 40 min per cycle, per IPC-7351B standards. For fracture investigation, the cross-sections of the samples are examined and analysed using the dye-and-pry technique and backscattered scanning electron microscopy. The packages' microstructures are characterized using an energy-dispersive X-ray spectroscopy approach. Also, the package assembly is investigated using the Darveaux numerical simulation method.

The study found that critical strain density is exhibited at the component pad/solder interface of the solder joint located at the most distant point from the axes of symmetry of the package assembly. The fracture mechanism is a crack fracture formed at the solder's exterior edges and grows across the joint's transverse section. It was established that Au content in the formed intermetallic compound greatly impacts fracture growth in the solder joint interface, with a composition above 5 Wt.% Au regarded as an unsafe level for reliability. The elongation of the crack is aided by the brittle nature of the Au-Sn interface through which the crack propagates. It is inferred that refining the solder matrix elemental compound can strengthen and improve the reliability of solder joints.

Inspection lead time and additional manufacturing expenses spent on investigating reliability issues in BGA solder joints can be reduced using the study's findings on understanding the solder joint fracture mechanism.

Limited studies exist on the thermal fracture mechanism of moisture-preconditioned BGA solder joints exposed to both multiple reflow and thermal cycling. This study applied both numerical and experimental techniques to examine the reliability issue.

This paper describes the different thickness measurement techniques that enable reliable thickness assessments, and the determination of the recommended immersion tin thickness for lead‐free soldering.

Immersion tin layers were prepared with systematically varying layer thicknesses. The samples were annealed at different reflow profiles, used in assembly for tin/silver/copper (SAC‐alloy) soldering. The layers were characterized with X‐ray fluorescence, electrochemical stripping coulometry, and by examining the cross sections using a scanning electron microscope. The solderability of the samples was determined with a solder balance (Solderability Tester Menisco ST60) using a SAC‐alloy (melting point 217°C) with T(max) at ΔT=28°C and ΔT=43°C above melting.

If all pure tin is converted into the Sn/Cu IMC, so that no pure tin is left as solderable layer, the wetting behaviour will decrease dramatically. Especially for multiple soldering processes, two times reflow followed by wave soldering, it is essential to have a pure tin layer covering the Sn/Cu IMC before going to the final soldering process. The required amount of residual pure tin over the Sn/Cu IMC is detailed in several papers. It is stated that a minimum of 0.2 μm of pure tin over the Sn/Cu IMC is absolutely necessary to ensure reliable wetting and solder joint formation. With the current immersion tin thickness recommendation of 1 μm, based on the needs of lead containing solder pastes, a residual pure tin layer will not be evident or thick enough to ensure reliable assembly for multiple soldering with lead‐free temperature profiles.

Helps to enable reliable thickness assessments, and the determination of the recommended immersion tin thickness for lead‐free soldering.

A new product design required the addition of a second layer of electronics to control a base module. This product was designed with significant overhangs of heavy leads and components which presented a significant challenge to many different solder assembly processes. Only the heated gas jet process was able to solder the product successfully without damaging the printed wiring boards.

To answer the challenge, a new machine was developed, combining dispensing of solder paste with hot gas jet reflow technology. This provided a combination of capabilities resulting in a flexible process which was significantly superior to alternative technologies.

Other soldering processes such as laser, focused xenon lamp, robotic soldering iron, and focused IR soldering technologies were evaluated. Each of these technologies causes some damage or defect to the assembly due to the heat sinking aspect of the circuit assembled. These alternative processes would create damage or defects to the assemblies by burning the laminate, delaminating the pads on the printed wiring board, or not soldering the pads.

Proof of concept tests before machine designs were initiated demonstrated the potential and capabilities of this technology for automated assembly soldering. Testing indicated that the heated gas jet processing would provide a means of soldering the assemblies at a controllable rate without damaging the circuit boards.

While evaluating the machine ion its design phase, a designed experiment was initiated to help understand the relationships between head temperature settings versus gas flow rates, the measurable output was time to reflow.

The process meets all expectations in terms of solder fillet appearance, volume, and overall visual quality while maintaining process cycle time requirements.

The purpose of this paper is to evaluate modeling of the reliability characteristics of the copper (Cu) used in plated through holes (PTHs) for electrical connections across printed circuit boards (PCBs).

Assessments of the Cu damage in the first three reflow cycles are performed using finite element analysis. A two‐dimensional axi‐symmetric model of a PTH on a laminate board is validated against a three‐dimensional full model and test cases. Stress and strain measurements in the inner ring of the PTH are obtained in numerical simulations.

Loads applied after the reflow cycles contribute to subsequent mechanical disconnects. Reliability assessments relying on undamaged circuits are less accurate than estimates incorporating Cu damage following three reflow cycles.

In order to increase the accuracy of PCB reliability predictions significantly, prior‐to‐use damage should be calculated. In this paper, a modification to the reliability analysis is proposed.

The purpose of this paper is to show production process developments and innovations that resolve many of the issues faced with certain process steps for printed circuit board (PCB) manufacturing following “green” practices.

Several key PCB manufacturing processes have been developed or studied with respect to new environmental legislations and practises.

The introduction of new legislations designed to protect the environment require changes to laminate materials, solders, and PCB manufacturing techniques. The effect of new laminate materials on the desmearing and metallising processes have been assessed and recommendations given. The effect of increased thermal stress on plated copper has been assessed. Developments in adhesion enhancement for black oxide alternatives have been made and are presented with their suitability for the newer green laminate materials. The development of a new laminate manufacturing technique to reduce environmental impact is introduced. The capabilities of different surface finishes in relation to new lead‐free soldering techniques is investigated and presented.

This is a short paper covering several major PCB processing steps and covers experiences and development results.

The paper details how “green” PCB manufacturing affects some key processes, developments to improve results and environmentally friendlier innovations in laminate manufacturing techniques.

This paper will review the challenges brought by lead‐free soldering and some preliminary experimental evaluation results will be discussed. The initial results show that the lead‐free soldering process with 260°C reflow peak temperature does not directly cause failures for bismaleimide‐triazine (BT)‐based fine pitch ball grid array (FPBGA) packages. However, the strict lead‐free soldering condition could degrade the integrity of weak interface joints and potentially damage the package in subsequent unbiased highly accelerated stress test (unbiased HAST) evaluation. The impacts of lead‐free soldering with high reflow temperature on concurrent available electronics components could be more severe than previously believed. In the future, new materials and design concepts should be applied to enhance the package reliability under strict lead‐free soldering conditions.

This paper reviews some continuing IBM study efforts conducted on surface mounted Leadless Chip Carrier (LCC) packaging for use in high density, high thermal stress military environments. The paper presents some designs, materials and solder joint processing considerations that can affect solder joint fatigue life. Also discussed are some thermal cycling test limitations, important properties of solder failure mechanisms and finally some technical concerns with both WS 6536E and DoD 2000 specifications as to their limitations with future surface mounted technologies.