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In the production of printed circuit assemblies, the demand for higher reliability levels has increased over the years. In order to achieve a high level of soldering quality, it is essential that solderability is built into the system at all stages and various factors must be taken into account. In the first section of this paper some of these factors are discussed. The various solderable coalings that are available are reviewed, some of the problems that can be encountered are illustrated and the effects of impurities in solders discussed. In the second part of the paper, the use of circuit boards having fused tin/lead coatings is discussed from the solderability point of view.

An overview has been presented on the topic of alternative surface finishes for package I/Os and circuit board features. Aspects of processability and solder joint reliability were described for the following coatings: baseline hot‐dipped, plated, and plated‐and‐fused 100Sn and Sn‐Pb coatings; Ni/Au; Pd, Ni/Pd, and Ni/Pd/Au finishes; and the recently marketed immersion Ag coatings. The Ni/Au coatings appear to provide the all‐around best options in terms of solderability protection and wire bondability. Nickel/Pd finishes offer a slightly reduced level of performance in these areas which is most likely due to variable Pd surface conditions. It is necessary to minimize dissolved Au or Pd contents in the solder material to prevent solder joint embrittlement. Ancillary aspects that include thickness measurement techniques; the importance of finish compatibility with conformal coatings and conductive adhesives; and the need for alternative finishes for the processing of non‐Pb bearing solders are discussed.

In the surface mount industry, microelectronic devices are reflow soldered to printed circuit boards with the benefit of mildly activated rosin (RMA) based fluxes. The residues from these fluxes, when not properly cleaned from the component boards, have been cited for decreased circuit life due to corrosion of the solder joints and loss of insulating resistance. Post‐solder cleaning operations with CFC (chlorofluorocarbon) solvents have been deemed environmentally harmful. Hence, there is a great need in the surface mount community for a no‐clean or fluxless solder reflow process. The BOC Group has developed a novel, proprietary process, by which circuit boards and their components are attached with a solder paste under a reactive fluxing atmosphere. The post‐solder residue is non‐corrosive and so minimal that it does not require a post‐solder cleaning operation. The solder joints exhibit good wetting, excellent joint strength and are essentially void‐free. Assembled circuits processed in this way meet all the criteria for ionic cleanliness and surface insulation resistance without post‐solder cleaning.

The emergence of new interconnection technologies involving double‐sided surface mounted components has put stronger restrictions on the method of preserving the solderable finish on printed circuit (PC) boards. The popular Sn/Pb coatings have come under strong scrutiny due to environmental hazards of lead and also because they do not provide flat, planar surfaces for SM assembly. Organic solderability preservative coatings (OSP) are emerging as strong contenders for replacing Sn/Pb surface finishes. Benzotriazole based organic coatings have been successfully used in the past by several electronics manufacturers. However, assembly technologies involving multiple thermal operations have necessitated a fundamental understanding of the thermal stabilities and the mechanism of corrosion protection provided by the OSPs. This paper reports the results of an investigation of the thermal stabilities of two organic corrosion protection coatings. Although both are organic azole based, they operate in two distinct regimes: one forming thin films (∼100 Å) and the other forming thick films (∼5000 Å). The mechanism of surface protection has been studied using direct surface analytical techniques such as X‐ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), scanning transmission electron microscopy (SEM/TEM) and Fourier transform infrared spectroscopy (FT‐IR). The solderability of the copper was measured by wetting balance techniques and correlated to the amount of copper oxidation. The results indicate that, although the thin films provide excellent protection for storage and handling operations, they decompose under heat, thereby causing oxidation of the copper. The thick films appear to withstand multiple thermal cycling. However, the underlying copper substrate can still be oxidised by oxygen diffusion through pores or cracks, or the film may undergo chemical changes that render the copper unsolderable.

Solder masks are used universally on high density printed circuit boards to reduce the occurrence of solder bridges between adjacent tracks and pads. The use of solder mask can, however, have a deleterious effect on the solderability, i.e., the solder pull‐through and top‐land wetting, of plated‐through‐hole boards. This work considers, quantitatively, the specific effect on PTH board solderability of solder mask, considering in turn the three classes of photoimageable dry film, photoimageable ink and screen printed ink. Two modes of solderability degradation have been identified: a geometrical effect that depends on the thickness of the mask and its encroachment around the solderable pads, and a contamination effect arising from the development and washing of the photoimageable masks from surfaces to be soldered subsequently.

This paper aims to evaluate the influence of previous exposure to moisture on delamination and formation of CAF (conductive anodic filament) in printed circuit boards used for lead‐free soldering.

The moisture absorption and desorption characteristics of printed circuit boards were evaluated according to the IPC/JEDEC J‐STD‐020C standard for handling of moisture sensitive components. The CAF test was performed according to IPC‐TM‐650, Test Method 2.6.25.

Printed circuit boards used for lead‐free soldering must be treated as moisture sensitive components. Severe delamination occurred on test boards that had been exposed to JEDEC level 1 conditions prior to soldering, while no delamination was observed on boards exposed to level 3. Furthermore, previous moisture and thermal exposure had a strong influence on CAF formation. The insulation resistance dropped three decades in less than 15 h in the worst case.

There are considerable stresses on printed circuit boards in lead‐free soldering processes. The influence from materials and processes is very large on the CAF formation. Therefore, a useful strategy is to evaluate the CAF properties for each supplier and material.

The paper pin‐points previous moisture exposure as a very important factor for delamination and CAF formation and confirms that printed circuit boards must be treated as moisture sensitive components.

The purpose of this paper was to analyse typical printed circuit board assemblies (PCBAs) processed by reflow, wave or selective wave soldering for typical levels of process-related residues, resulting from a specific or combination of soldering processes. Typical solder flux residue distribution pattern, composition and concentration are profiled and reported. The effect of such contaminants on conformal coating was tested.

Presence of localized flux residues was visualized using a commercial residue reliability assessment testing gel test and chemical structure was identified by Fourier transform infrared spectroscopy, while the concentration was measured using ion chromatography, and the electrical properties of the extracts were determined by measuring the leak current using a twin platinum electrode set-up. Localized extraction of residue was carried out using a commercial critical contamination control extraction system.

Results clearly show that the amount and distribution of flux residues are a function of the soldering process, and the level can be reduced by an appropriate cleaning. Selective soldering process generates significantly higher levels of residues compared to the wave and reflow process. For conformal coated PCBAs, the contamination levels generated from the tested wave and selective soldering process are found to be enough to generate blisters under exposure to high humidity levels.

Although it is generally known that different soldering processes can introduce contamination on the PCBA surface, compromising its cleanliness, no systematic work is reported investigating the relative levels of residue introduced by various soldering processes and its effect on corrosion reliability.

A new corrosion test for assessing flux residues is applied to marginally cleaned water soluble fluxed test boards and low solids/no clean fluxed test boards. This test method developed by Bono has been modified to accelerate the corrosion process. The corrosion mechanism observed in this study is conductive anodic filament (CAF), a corrosion mechanism proposed in 1979 by Lando et al. It is postulated that this degradation mechanism is due to the high bias voltage (190 V) coupled with the high humidity (85%) and high temperature (85°C) conditions used in this test. Important parameters in the test method are discussed and recommended refinements are given.

The printed circuit board version, ‘packlayer’, represents an alternative to printed circuit boards with conventional solder mask systems which is not yet widely known. This alternative type does, however, offer some considerable advantages in comparison with printed circuit boards with solder resist, with the result that the higher cost involved is thoroughly acceptable. Through the development of a new system called ‘Low‐Cost‐Packlayer’, bearing the special name MeSoMask, a variant has emerged within the packlayer sector. This special version combines the advantages of the packlayer with the costs of a conventional solder resist system and therefore presents a genuine alternative to the normal printed circuit board.

The potentially highly automated process of surface mounting electronic components directly onto a substrate or printed circuit board possesses a very weak link. Component movement subsequent to placement and before or during solder reflow leads to defect conditions such as tombstoning or rotational misalignment. This work investigates the feasibility of replacing this ‘weak’ assembly step(s) with ultrasonics. The selection and modification of suitable ultrasonic equipment is described as in the bonding of chip components onto PCBs. Reliability analysis of the resultant bonds along with bond quality in terms of shear strength and appearance under scanning electron microscope and optical microscope is studied. The results show that, with certain preferred directions of ultrasonic weld, weld preload and weld time bond strengths obtained compare very favourably with those achieved with the present surface mount technology reflow process, hence establishing the feasibility of ultrasonics for this application.