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Modern wireless communications need novel microwave components that can be effectively used for high data rate and low-power applications. The operating environment decides the severity of the noise coupled to the transceiver system from the ambient environment. In a deep fading environment, narrowband systems fail where the wideband systems come for rescue. Thus, the microwave components are ought to switch between the narrowband and wideband states. This paper aims to study the design of a bandpass filter to meet the requirements by appropriately switching between the dual narrowband frequencies and single ultra-wideband frequency band.

The design and implementation of a compact microwave filter with reconfigurable bandwidth characteristics are presented in this paper. The proposed filter is constructed using a hexagonal ring with shorted perturbation along one corner. The filter is capacitively coupled to the external excitation source. External stubs are connected to the corners of the hexagonal resonator to obtain dual passband characteristics centred at 2.1 and 4.5 GHz. The external stubs are configured to achieve bandwidth reconfigurable characteristics. PIN diodes are used with a suitable biasing network to obtain reconfiguration. In the reconfigured state, the proposed two-port filter offers a continuous bandwidth from 2.1 to 5.9 GHz. The roll-off rate along the band edges is improved by increasing the order of the filter.

The proposed filter operates in two states. In state 1, the filter operates with dual frequencies centred around 2 and 4.5 GHz with insertion loss less than <1 dB and return loss greater than 13 dB with a peak return loss of 21 and 31 dB at 2.1 and 2.15 GHz, respectively. In state 2, the filter operates from 2.1 to 5.9 GHz with insertion loss less than 1 dB and return loss greater than 12 dB. The filter exhibits four-pole characteristics with a peak return loss greater than 22 dB. Thus, the fractional bandwidth of the proposed filter is 17% and 16% in state 1, whereas the fractional bandwidth is 95% in state 2.

The proposed filter is the first of its kind to simultaneously offer miniaturization and bandwidth reconfiguration. The proposed second-order filter has two-pole characteristics in the narrowband state, whereas four-pole characteristics are realized in the wideband state. The growing interest in 4G and 5G wireless communications makes the proposed filter a suitable candidate for operation in the rich scattering environment.

Digital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization.

The distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324.

The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively.

The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.

Filter design plays an essential role in most communication standards. The essential element of the software-defined radio is a channelizer that comprises several channel filters. Designing filters with lower complexity, minimized area and enhanced speed is a demanding task in currently prevailing communication standards. This study aims to propose an efficient reconfigurable residue number system (RNS)-based multiply-accumulate (MAC) channel filter for software radio receivers.

RNS-based pipelined MAC module for the realization of channel finite impulse response (FIR) filter architecture is considered in this work. Further, the use of a single adder and single multiplier for realizing the filter architecture regardless of the number of taps offers effective resource sharing. This design provides significant improvement in speed of operation as well as a reduction in area complexity.

In this paper, two major tasks have been considered: first, the RNS number conversion is performed in which the integer is converted into several residues. These residues are processed in parallel and are applied to the MAC-FIR filter architecture. Second, the MAC filter architecture involves pipelining, which enhances the speed of operation to a significant extent. Also, the time-sharing-based design incorporates a single partial product-based shift and add multiplier and single adder, which provide a low complex design. The results show that the proposed 16-tap RNS-based pipelined MAC sub-filter achieves significant improvement in speed as well as 89.87% area optimization when examined with the conventional RNS-based FIR filter structure.

The proposed MAC-FIR filter architecture provides good performance in terms of complexity and speed of operation because of the use of the RNS scheme with pipelining and partial product-based shift and adds multiplier and single adder when examining with the conventional designs. The reported architecture can be used in software radios.

In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters.

The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer.

Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively.

The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

This paper aims to concentrate on an efficient finite impulse response (FIR) filter architecture in combination with the differential evolution ant colony algorithm (DE-ACO). For the design of FIR filter, the evolutionary algorithm (EA) is found to be very efficient because of its non-conventional, nonlinear, multi-modal and non-differentiable nature. While focusing with frequency domain specifications, most of the EA techniques described with the existing systems diverge from the power related matters.

The FIR filters are extensively used for many low power, low complexities, less area and high speed digital signal processing applications. In the existing systems, various FIR filters have been proposed to focus on the above criterion.

In the proposed method, a novel DE-ACO is used to design the FIR filter. It focuses on satisfying the economic power utilization and also the specifications in the frequency domain.

The proposed DE-ACO gives outstanding performance with a strong ability to find optimal solution, and it has got quick convergence speed. The proposed method also uses the Software integrated synthesis environment (ISE) project navigator (p.28xd) for the simulation of FIR filter based on DE-ACO techniques.

This paper is aimed to study the design of a miniaturized filter with tri-band characteristics. In this paper, perturbation is used to realize circuit miniaturization and multi-band by exploiting the inductive property. During this process, vias are added for twofold benefit, namely, circuit miniaturization and enhanced frequency selectivity at high frequency. Thus, with the introduction of the shorting via, the single-band dual-mode bandpass filter is converted into a tri-band filter with a smaller electrical size.

This paper presents the design and characterization of a miniaturized two-port filter with tri-band operating characteristics. The proposed filter is constructed using a square patch resonator operating at 5.2 GHz with a capacitively coupled feed configuration. A square perturbation is added to the corner of the square patch to achieve diagonal symmetry and to excite dual mode. The perturbation offers a sharp transmission zero defining bandwidth of the proposed filter. In addition, a shorting post is introduced to achieve an 88% size reduction by lowering the operating frequency to 1.8 GHz.

The prototype filter has insertion less than 1.2 dB and return loss better than 12 dB throughout all the realized frequency bands. The prototype filter is fabricated and the simulation results are validated using experimental measurements. The realized fractional bandwidths of the proposed bandpass filter are 11/5.6/1 at 1.8/4.6/5.85 GHz, respectively. The quality factor of the proposed antenna is greater than 80 and a peak Q-factor of 387 is realized at 5.85 GHz. The high Q-factor indicates low loss and improved selectivity. The rejection levels in the stopband are greater than 20 dB.

The results indicate that the proposed filter is a suitable choice for low-power small-scale wireless systems operating in the microwave bands. The realized filter has the smallest footprint of 0.36λ_eff  × 0.19λ_eff where λ_eff is the effective wavelength calculated at the lowest frequency of operation.

Finite impulse response (FIR) digital filters are a general element in several digital signal processing (DSP) systems. In VLSI platform, FIR is a developing filter because the complexity of design grows with the length of the FIR filter and also it has less latency. Generally, the FIR filter is designed dominated by the multiplier and adder. The conventional FIR filters occupy more area because of several numbers of adders and multipliers for filter designs.

To overcome this issue, the Vedic Multiplier (VM) and Moore-based LoopBack Adder (MLBA) approach-based optimal FIR filter were designed in this research. Normally, the coefficient has been generated manually, which performs the FIR filter operation. So, the coefficient was generated from the MATLAB filter design and analysis tool. All pass coefficient was introduced in this research, which performs the processing element (PE). The VM approach was utilized in the PE to multiply the filter inputs and coefficients. This research employs the Moore-based LBA (MLBA) in the accumulator for the adding output of the PE. An MLBA approach is a significantly reduced area and increases speed by applying a looping transform function. Here, the proposed method is called a VM-MLBA-FIR filter. In this research, the FIR filter was done in Field Programmable Gate Array (FPGA) Xilinx by using Verilog code on various Virtex devices.

The experiment results showed that VM-MLBA-FIR filter reduced 26.88% of device utilization and 0.32 W of minimum power consumption compared to the existing PSA-FIR filter.

The experiment results showed that VM-MLBA-FIR filter reduced 26.88% of device utilization and 0.32 W of minimum power consumption compared to the existing PSA-FIR filter.

This study aims to design a compact filtering monopole antenna for 5G communication. The design is most suited for various applications within the frequency range of 2.2–3.8 GHz. It offers enhanced bandwidth and reasonable gain with wide-stopband performance.

A low-pass filter (LPF) of complementary split ring resonator (CSRR) with short-circuited stub lines is integrated with a compact defected coplanar waveguide fed truncated circular monopole ultrawideband (UWB) antenna. The reference UWB antenna etched on an FR4 substrate was coupled to the designed LPF to transform the UWB antenna into a wideband antenna. The effect of coupling is analyzed based on the real and imaginary responses of the terminal impedance (ZT) curve. Three short-circuited stub lines of asymmetric lengths are added to the CSRR LPF to suppress harmonics, thereby enhancing the stopband performance and impedance matching between the elements. The proposed filtering antenna is fabricated using a photolithography process, and the corresponding results are measured using a network analyzer (N9951A). The radiation parameters of the proposed filtering monopole antenna are tested in the anechoic chamber. The simulated/measured results are compared and are found in agreement with each other.

The proposed design suppresses 6.5f0 harmonics, resulting in wide stopband performance and increased gain selectivity at the transition edge. A peak suppression of −41 dB and an average suppression of −18 dB were attained throughout the stopband. An operating fractional bandwidth of 54.5%/143% with a peak gain of 3 dBi/5 dBi was obtained. The proposed filtering antenna supports 5G applications such as WiMAX, WLAN, n7, n38 IMT-E, n30 WCS, n40 TDD, n41 TDD, n48 TDD, n78 TDD and n90 TDD.

The proposed design is novel and compact and has a wide application in 5G communication. With the filter, the antenna operates in wideband, and without the filter, it operates in UWB. Besides, it offers enhanced stopband performance with high gain selectivity at the transition edge. Comparatively, a 50% improvement in bandwidth, 52% improvement in size reduction and 33% improvement in harmonic suppression are attained.

This paper aims to design a dual mode X-band substrate integrated waveguide (SIW) bandpass filter in the conventional SIW structure. A pair of back-to-back square and split ring resonator is introduced in the single-layer SIW bandpass filter. The various coupling configurations of SIW bandpass filter using split square ring slot resonator is designed to obtain dual resonant mode in the passband. It is shown that the measured results agree with the simulated results to meet compact size, lower the transmission coefficient, better reflection coefficient, sharp sideband rejection and minimal group delay.

A spurious suppression of wideband response is suppressed using an open stub in the transmission line. The width and length of the stub are tuned to suppress the wideband spurs in the stopband. The measured 3 dB bandwidth is from 8.76 to 14.24 GHz with a fractional bandwidth of 48.04% at a center frequency of 11.63 GHz, 12.59 GHz. The structure is analyzed using the equivalent circuit model, and the simulated analysis is based on an advanced design system software.

This paper discusses the characteristics of resonator below the waveguide cut-off frequency with their working principles and applications. Considering the difficulties in combining the resonators with a metallic waveguide, a new guided wave structure – the SIW is designed, which is synthesized on a planar substrate with linear periodic arrays of metallized via based on the printed circuit board.

This study has investigated the wave propagation problem of the SIW loaded by square ring slot-loaded resonator. The electric dipole nature of the resonator has been used to achieve a forward passband in a waveguide environment. The proposed filters have numerous advantages such as high-quality factor, low insertion loss, easy to integrate with the other planar circuits and, most importantly, compact size.