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The aim of this paper is to analyze the effects of aggressor‐line load variations (both active gate and passive capacitive loads) on the non‐ideal effects of a coupled VLSI‐interconnect system.

Signal delay, power dissipation and crosstalk noise in interconnect can be influenced by variation in load of another interconnect which is coupled to it. For active gate and passive capacitive load variations, such effects are studied through SPICE simulations of a coupled interconnect pair in a 0.13 μm technology. Crosstalk between a coupled pair, is affected by transition time of the coupled signal, interconnect length, distance between interconnects, size of driver and receiver, pattern of input, direction of flow of signal and clock skew. In this work, influence of an aggressor‐line load variations (both active gate and passive capacitive loads) on the non‐ideal effects of delay, power consumption and crosstalk in a victim‐line of a coupled VLSI‐interconnect system are determined through SPICE simulation. In this experiment, the victim line is terminated by a fixed capacitive load and the coupled to aggressor line has variable load, either passive capacitive or active gate. Four different input signal cases have been considered for the two types of variable load. Distributed RLC transmission model of interconnect is considered for the SPICE simulations.

The simulation results reveal that the effects are much dependent on the type of load and signal variations at the inputs of the two mutually coupled interconnects. Load control at the aggressor far end can be used to minimize some of the adverse effects of crosstalk.

This paper shows that in interconnect, signal delay, power consumption and crosstalk are all affected by load variations in a coupled neighboring interconnect.

In this paper output voltage waveform of CMOS repeater driven VLSI long interconnects is analysed, for deep submicron technologies. Ramp inputs are considered in the analysis as these are more practical than step inputs.

Analytical models are developed for the time dependence of output voltage of repeater driven interconnect loads for rising as well as falling ramp input signals. The interconnect is modelled as a resistive‐capacitive load. Various operating regions of the MOSFETs are considered in the models. Method has also been given for determining the time at which MOSFET transits from saturation to linear region.

A good agreement between the analytical and SPICE results is obtained, with analytical error 3 per cent at the most. The models developed work accurately for scaled‐supply voltages too. For a repeater loaded interconnect the variation of 90 per cent delay with number of repeaters at different supply voltages has also been determined by the proposed model. It is found that the optimum number of repeaters decreases with voltage‐scaling and this decrease is technology independent.

The parasitic inductance component in long interconnects is not considered in this analysis.

The work is useful for timing analysis of repeater driven resistive interconnects.

A very concise analytical approach for a CMOS repeater stage timing analysis is developed.

Delay and power dissipation are the two major design constraints in very large scale integration (VLSI) circuits. These arise due to millions of active devices and interconnections connecting this gigantic number of devices on the chip. Important technique of repeater insertion in long interconnections to reduce delay in VLSI circuits has been reported during the last two decades. This paper deals with delay, power dissipation and the role of voltage‐scaling in repeaters loaded long interconnects in VLSI circuits for low power environment.

Trade off between delay and power dissipation in repeaters inserted long interconnects has been reviewed here with a bibliographic survey. SPICE simulations have been used to validate the findings.

Optimum number of uniform sized CMOS repeaters inserted in long interconnects, lead to delay minimization. Voltage‐scaling is highly effective in reduction of power dissipation in repeaters loaded long interconnects. The new finding given here is that optimum number of repeaters required for delay minimization decreases with voltage‐scaling. This leads to area and further power saving.

The bibliographic survey needs to be revised in future, taking the various other aspects of VLSI interconnects viz. noise, cross talk extra into account.

The paper is of high significance in VLSI design and low‐power high‐speed applications. It is also valuable for new researchers in this emerging field.

In this short communication, transition times of input signals for various stages of a repeater‐chain loaded VLSI interconnects are studied.

SPICE simulations.

It is observed that for a fixed number of repeaters a smaller load will reduce transition time. The effect is not very significant, if the load is moderate.

Method can be very useful for short‐circuit power estimation in repeater‐chains.

To study the effect of voltage‐scaling on output voltage waveform, delay and power dissipation in a single inverter/repeater driven interconnect load, in different technology nodes.

An analytical expression for the output voltage of a single CMOS‐inverter/repeater driven long interconnects is developed. Delay analysis by the use of this expression, for long interconnects, modeled as RLC load, is compared with SPICE simulations. Good agreement between analytical and SPICE derived results is obtained.

The model works well for both sub‐micron and nanometer CMOS technologies. The maximum error in 90 percent fall time of output voltage is 7.5, 2.6 and 0.28 percent in 0.8 μm, 0.18 μm and 70 nm technologies, respectively. The maximum inaccuracy in case of high to low 50 percent propagation delay is about 5 percent for 0.8 μm, 3.1 percent for 0.18 μm and 2.3 percent in case of 70 nm technologies. The model shows a very good accuracy for nanometer technologies. The analysis shows that the use of scaled technologies along with voltage‐scaling leads to significant saving in power as well as delay improvement of a repeater driven long interconnect.

A new compact analytical expression for the output voltage of a single CMOS‐inverter driven long RLC interconnects is developed. The analysis carried out in the paper is of value to low‐power VLSI interconnect design.