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This paper aims to detail the qualification of alternative substrate materials and reliability aspects for quad flat no lead (QFN) packages for highly stressed electronic devices, e.g. for use in automotive applications.

Detailed information is given on the advanced climatic and mechanical requirements that electronic devices have to withstand during life cycle testing to qualify for the automotive industry. Studies on the suitability of high‐temperature thermoplastics as substrate materials for printed circuit boards and the qualification of QFN packages for advanced requirements are described. In addition, information on cause‐effect relationships between thermal and vibration testing are given.

With respect to adhesion of metallization on high‐temperature thermoplastics and the long‐term stability of the solder joints, these substrate materials offer potential for use in electronic devices for advanced requirements. In addition, the long‐term stability of the solder joints of QFN packages depends on the design of the landings on the PCB and the separation process of the components during manufacturing.

The paper covers only a selection of possible high‐temperature thermoplastic materials that can be used in electronics production. Also, this paper has a focus on the new packaging type, QFN, in the context of qualification and automotive standards.

The paper details the requirements electronic devices have to meet to be qualified for the automotive industry. Therefore, this contribution has its value in giving information on possible substrate alternatives and the suitability for the usage of QFN components for highly stressed electronic devices.

Solder paste printing is the most common method for attaching surface mount devices to printed circuit boards (PCB), and it has been reported that a majority of all assembly defects occur during the stencil printing process. It is also recognized that the solder paste printing process is wholly responsible for the solder joint formation of leadless package technologies such as land grid array (LGA) and quad-flat no-lead (QFN) components and therefore is a determining factor in the long-term reliability of said devices. The aim of this experiment is to determine the acceptable lower limit for solder paste volume deposit tolerances during stencil printing process to ensure both good assembly yield and reliability expectations.

Stencils with modified aperture dimensions at particular locations for LGA and QFN package footprints were designed to vary the solder paste volume deposited during the stencil printing process. Solder paste volumes were measured using solder paste inspection system. Low volume solder paste deposits were generated using the modified stencil designs to evaluate assemble yield. Accelerated thermal cycling (ATC) was used to determine the reliability of the solder joints. Failure analysis was used to determine if the failure was attributed to the low paste volume locations.

Solder joints formed with nominal paste volume survived longer in ATC compared to intentionally low volume joints. Transfer efficiency numbers for both good assembly yield and good reliability are reported for LGA and QFN devices. A lower volume limit is reported for leadless devices that should not significantly affect yield and reliability in thermal cycling.

Very little literature is available on solder paste volume tolerance limits in terms of assembly yield and reliability. Manufacturers often use ±50 or ±30 per cent of stencil aperture volume with no evidence of its effectiveness in determining yield and reliability of the solder joints.

The purpose of this paper is to employ data mining as a new diagnosing scheme for investigating void formation to the thermal pad in quad flat non‐lead (QFN) assembly. Occurrences of voiding in various scenarios of component design, materials selection and manufacturing process are analyzed.

This research investigates the process yield of a PCB assembly for a handheld device in the electronics manufacturing industry using the chi‐square automatic interaction detection (CHAID) algorithm and chi‐square test. Practical data generated by an X‐ray apparatus from the shop floor are collected. The critical attributes to the void formation (in the solder joint) of the QFN component are identified.

Stocking the PCB material beyond ten days may increase the level of voiding by 1%. Using PCB provided by vendor U helps decrease the level of voiding by 1.6%. Stocking the component material above 43 days may increase the level of voiding by 1.9%. In addition, reflow soldering profile with time above liquid (TAL) less than or equal to 62 sec and with peak temperature higher than or equal to 241°C generate less voids. Finally, the via‐in‐pad design causes a concave geometry on the surface of thermal pad which contributes to the voiding formation. The amount of voiding can be further diminished by plugging the via with plated copper.

This research implements CHAID that extracts useful knowledge from a huge amount of manufacturing data in order to realize the complex interaction effects through automated analysis. The extent of voiding in the samples using the optimal process suggested through CHAID algorithm can be reduced from 16% to 10.2%.

This paper aims to propose an innovative parametric design for artificial neural network (ANN) modeling for the multi-quality function problem to determine the optimal process scenarios.

The innovative hybrid algorithm gray relational analysis (GRA)-ANN and the GRA-Entropy are proposed to effectively solve the multi-response optimization problem.

Both the GRA-ANN and the GRA-Entropy analytical approaches find that the optimal process scenario is a stencil aperture of 57 per cent and immediate processing of the printed circuit board after exposure to a room environment.

A six-week confirmation test indicates that the optimal process has improved quad flat non-lead assembly yield from 99.12 to 99.78 per cent.

The vacuum vapour phase soldering method was investigated by numerical simulations. The purpose of this study was to examine the temperature changes of the solder joints during the vapour suctioning process. A low pressure is used to enhance the outgassing of the trapped gas within the solder joints, which otherwise could form voids. However, the system loses heat near the suction pipe during the suctioning process, and it can result in preliminary solidification of the solder joints before the gas could escape.

A three-dimensional numerical flow model based on the Reynolds averaged Navier–Stokes equations with the standard k-e turbulence method was developed. The effect of the vapour suctioning on the convective heat transfer mechanism was described by the model. Temperature change of the solder joints was studied at the mostly used substrate and component combinations, as well as at different system settings.

In the function of the substrate thickness and the component size, the solder joints can lose large amount of heat during the void reduction process, which leads to preliminary solidification before the entrapped gas voids could be removed.

The results provide setting information of vacuum vapour phase technology for appropriate and optimal applications.

The relationship between low pressure generation and convective heat transfer mechanism during vacuum vapour phase soldering has not been studied yet. The possible negative effects of the vapour suctioning process on the solder joint temperature are unknown.

The purpose of this paper is to evaluate and compare the effectiveness and sensitivity of different cleanliness verification tests for post soldered printed circuit board assemblies (PCBAs) to provide an understanding of current industry practice for ionic contamination detection limits.

PCBAs were subjected to different flux residue cleaning dwell times and cleanliness levels were verified with resistivity of solvent extract, critical cleanliness control (C3) test, and ion chromatography analyses to provide results capable of differentiating different sensitivity levels for each test.

This study provides an understanding of current industry practice for ionic contamination detection using verification tests with different detection sensitivity levels. Some of the available cleanliness monitoring systems, particularly at critical areas of circuitry that are prone to product failure and residue entrapment, may have been overlooked.

Only Sn/Pb, clean type flux residue was evaluated. Thus, the current study was not an all encompassing project that is representative of other chemistry‐based flux residues.

The paper provides a reference that can be used to determine the most suitable and effective verification test for the detection of ionic contamination on PCBAs.

Flux residue‐related problems have long existed in the industry. The findings presented in this paper give a basic understanding to PCBA manufacturers when they are trying to choose the most suitable and effective verification test for the detection of ionic contamination on their products. Hence, the negative impact of flux residue on the respective product's long‐term reliability and performance can be minimized and monitored effectively.

This research aims to study the stencil printing process of the quad flat package (QFP) component with a pin pitch of 0.4 mm. After the optimization of the printing process, the desired inspection specification is determined to reduce the expected total process loss.

Static Taguchi parametric design is applied while considering the noise factors possibly affecting the printing quality in the production environment. The Taguchi quality loss function model is then proposed to evaluate the two types of inspection strategies.

The optimal parameter-level treatment for the solder paste printing process includes a squeegee pressure of 11 kg, a stencil snap-off of 0.14 mm, a cleaning frequency of the stencil once per printing and using an air gun after stencil wiping. The optimal upper and lower specification limits are 119.8 µm and 110.3 µm, respectively.

Noise factors in the production environment are considered to determine the optimal printing process. For specific components, the specification is established as a basis for subsequent processes or reworks.

This study aims to focus on the passive components of System in Package SiP modules and discusses the geometric pad designs for 01005-sized passive components, the front end design of the hole size and shape of the stencil and the parameters of the stencil sidewall coating, to determine the optimum parameter combination.

This study plans and conducts experiments, where a L8(27) inner orthogonal array is built to consider the control factors, including a L4(23) outer orthogonal array to consider the noise factor, and the experimental data are analyzed by using the technique for order preference by similarity to ideal solution multi-quality analysis method.

The results show that the optimum design parameter level combination is that the solder mask opening pad has no solder mask in the lower part of the component, the pad width is 1.1 times that of the component width, the pad length is 1.75 times that of the electrode tip length, the pad spacing is 5 mil, the stencil open area is 90% of the pad area, the stencil opening corner has a 3 mil chamfer angle, and the stencil sidewall is free of nano-coating.

The parameter design and multi-quality analysis method, as proposed in this study, can effectively develop the layout of passive components on a high-density SiP module substrate, to stabilize the process and increase the production yield.

This paper aims to discuss the key factors affecting the quality characteristics, such as the number of solder balls, the spread distance of residual underfill and the completion time of the underfilling.

The Taguchi method is applied to configure the orthogonal table and schedule and execute the experiment. In addition, principal components analysis is used to obtain the points. Then, based on gray relational analysis and the technique for order preference by similarity to ideal solution, the closeness between each quality characteristic and the ideal solution is adopted as the basis for evaluating the quality characteristics.

The optimal parameter combination is proposed, which includes 4 dispensing (11 mg/dispensing), a “half flow” interval state, 80°C preheating module PCB board and an L-shaped dispensing path and verification testing is performed.

For vehicles and handheld electronic products, solder joints that connect electronic components to printed circuit boards may be cracked due to collision, vibration or falling. Consequently, solder balls are closely surrounded and protected by the underfill to improve joint strength and resist external force factors, such as collision and vibration. This paper addresses the defects caused during the second reflow process of a vehicle electronic communication module after the underfilling process.

The purpose of this paper is to determine the overall free convective heat transfer coefficient for an assembly constituted by a Quad Flat Non-lead QFN16 welded on a Printed Circuit Board (PCB) which may be inclined with respect to the horizontal plane by an angle varying between 0° and 90° corresponding to the horizontal and vertical position, respectively. This electronic device widely used in electronics generates during its effective operation a power ranging from 0.1 to 0.8 W. The assembly is installed in an air-filled cavity.

Calculations are done by means of the finite volume method for many configurations obtained by varying the generated power, the inclination angle and the position of the QFN16 on the PCB. The dynamic and thermal aspects are presented and commented.

The study shows that the thermal state of the electronic device is influenced by the previous three physical parameters. A correlation between the global convective exchange coefficient, the generated power and the PCB inclination angle is proposed in this survey.

The results of this survey allow a better thermal control of this conventional arrangement widely used in electronic applications.

The correlations proposed in this work are original and unpublished. The considered power varies between 0.1 and 0.8W corresponding to the effective operation of the device, associated to a PCB inclination angle ranging between 0° and 90°.