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High density packaging mounted VLSI demand highly dense and highly accurate multilayer printed wiring boards. The authors have studied Ultra Thin Copper (UTC) technology of printed wiring boards for application to the packages of high speed and high performance computers for more than 10 years. This paper describes the requirement for fine line and highly dense multilayer printed wiring boards and the study of the development of a suitable process using the UTC. The discussions include the behaviour of pattern etching and effects of plating thickness, the improvement of plating thickness uniformity, the selection of carrier types, the measurement of peel strength between copper foil and substrate, and so on. The UTC application reduces the defects caused by surface contamination of epoxy resin. Degradation of surface resistance is also discussed, which may be caused by surface creeping of alkaline ions arising from residues of plating solution within the plated‐through hole wall. These investigations could establish UTC technology for fine line printed wiring boards.

In this issue of the Journal we continue with our series on National and International Committees for Printed Wiring by examining the work carried out by the Printed Wiring and Associated Techniques Committee (PW) of the Electronic Engineering Association (EEA).

It is often necessary to estimate the number of board layers in electronic modules before detailed routing is possible. Several methods for estimating board interconnect requirements prior to the existence of a netlist have been developed. Some estimation approaches depend on the use of heuristics derived from studying actually routed designs, while others depend on geometric or statistical arguments. The applicability and uncertainties associated with these estimation techniques are not widely understood. In this paper several different routing estimation methods are applied to a variety of printed wiring board and multichip module applications. The accuracy with which the methods predict the amount of required wiring is compared.

New requirements for printed wiring base materials were announced by the Underwriters Laboratories, Inc. They will impact on the OEM, the printed wiring manufacturer, and his base material suppliers. This paper presents an overview of past and present base material requirements, followed by the rationale and specifics of the augmented criteria. Action required by the printed wiring manufacturer to comply with these new UL 796 Standard revisions is explained.

A new treatment method for the copper innerlayers of polyimide multilayer printed wiring boards has been developed. Conventional oxide coatings experience acid penetration through the bonding interface during through‐hole plating pretreatment. This problem was eliminated by substitution of metallic copper for the surface oxide. Promotion of the copper innerlayer adhesion to the prepreg by the oxide coating was based upon a mechanical interlocking effect caused by the minute roughness of the oxide crystals. Reduction treatment of the surface oxide layer was found to give a metallic copper surface with no changes in its morphology. Adhesion strength of polyimide prepregs to copper foils after the reduction treatment was equivalent to that of the original brown oxide coating. Acid resistance was enhanced by elimination of the oxide layer from the bonding interface. The reduction treatment, combined with the conventional oxide coating technique, can realise high density multilayer printed wiring boards with greater reliability and performance.

This paper reveals a new methodology for predicting the most efficient design rules to follow for high density printed wiring boards prior to physical layout. The only input is from a schematic diagram, parts list and proposed board size. The methodology attempts to a priori determine the wiring capabilities of different PWB designs for a given product application. The particular focus is the difference between through‐hole and HDI designs.

In the assembly process of high reliability printed wiring boards (PWBs), rework cycles seem to be an unfortunate fact of life. The question repeatedly arises as to how many times a solder joint incorporating plated‐through‐holes (PTHs) can be reworked without degrading the configuration. By performing a controlled experiment, the authors were able to answer that question and make recommendations as to the limits that should be placed on the number of reworks. They were further able to look at the following factors: operators, board type, number of layers and solder temperature to determine which were the most significant in determining limits to the number of rework cycles. The results showed that the more layers the board contained, the more at risk the PTH was to rework‐induced defects. This perhaps defies conventional wisdom that the board type or temperatures were the driving contributors. The increased number of board layers corresponds to thinner dielectric layers. The experimental results were repeated in a theoretical review using a finite element analysis (FEA) model that was developed showing the thermally induced stresses in the solder joint and PTH region. For multilayer boards, it is recommended that rework be limited to three cycles. The present work shows that there is evidence of degradation by the fifth cycle on boards with thinner dielectric (10‐layer board, dielectric thickness 0.008 in.). By limiting the number of reworks, the risk of inducing failure mechanisms into PWAs (printed wiring assemblies) is dramatically reduced.

In the last decade through‐hole mounting to printed wiring boards has matured and people now have the tools to diagnose and correct any solderability problems which might arise. Such is not the case with surface mount soldering technology. In surface mount the connections are smaller and are often hidden from view. Therefore when a solderability problem does occur it may never be known until the assembly fails. The solution to the situation is to understand the nature of the problems and provide assurance that they will not occur during assembly soldering. This paper is structured in two parts. The first details the types of solderability problems unique to surface mounting. Examples of these problems will be shown and discussed with reference to solder joint life. The second part of the paper discusses the solderability testing of surface mount devices and printed wiring boards intended for surface mounting. This discussion will concentrate on the new quantitative solderability test methods being developed in this company's laboratory for leadless devices and printed wiring boards. As part of this development, new solderability criteria have been defined which reflect the unique problems associated with surface mounting.

This paper is an examination of residues on printed wiring boards and printed wiring assemblies. Sources of residues are illustrated and the effects of various residues are discussed. Case studies are presented for bare board cleanliness issues, water soluble flux and aqueous cleaning processes, and low solids flux (no‐clean) processes, with and without cleaning. The case studies reflect lessons learned in various process troubleshooting efforts. Residues in this paper were characterized using advanced ion chromatography procedures. In addition, some data on surface insulation resistance (SIR) are presented.

Emerging ‘chip‐size’ packages, and bare flip‐chips, require new substrate properties if high lead count chips are to be reliably interconnected on printed wiring boards and multichip modules at low cost. Blind via holes have been shown to increase interconnect density significantly without adding layers which contribute to high cost. Until recently, the use of blind vias has been limited to high‐end applications since standard fabrication methods, either sequential lamination or controlled depth drilling, are too slow and expensive for most high volume commercial applications. To maintain a low layer count while interconnecting higher I/O packages, commercial and consumer electronics require a substrate technology which supports high speed, micro‐via hole formation. This paper describes a process for fabricating high speed micro‐vias in dimensionally stable non‐woven Aramid reinforced laminates using laser ablation technology. Laser equipment capable of producing over 100 blind micro‐via holes per second is discussed. The process steps of hole cleaning and plating are reviewed, showing how existing PWB manufacturing technologies can be used. This process is compared with other methods of generating small holes and blind vias in printed wiring boards. In addition, requirements for flip‐chip and chip‐size packages, including a coefficient of thermal expansion of <10 ppm/°C and thin laminate dimensional stability of <0.03%, are explained.