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It was observed that “no solder” or “skipped solder” defects occurred on a particular printed circuit board assembly product during wave soldering. Investigations were carried out to find out the cause of this defect and to recommend an optimal hot air level coating thickness. To evaluate whether thicker plating helps to produce better solderability, new printed circuit boards with an average plating thickness of 4.27 μm were sent for solderability testing. This increase in plating thickness resulted in no defects in the solderability test. This is in contrast to the current printed circuit board that had a no/skipped solder defect rate of 1,433 ppm due to the thinner plating thickness which was in the region of 2.26 μm. In summary, the investigations made have revealed imperfections in the pad plating, and it is recommended that a thicker or more even plating is achieved during the hot air levelling process at the printed circuit board manufacturing site so as to eliminate no/skipped solder defects that are induced by this printed circuit board deficiency.

Discusses the manufacturing technology associated with the assembly of printed circuit boards [PCBs] covering photolithography, etching, manual assembly of PCBs and the soldering methods involved. Describes how all the stages of PCB assembly can be automated and also looks at how the boards are cleaned and tested. Concludes that many factors need to be taken into account when deciding which method of manufacturing printed circuits would be best suited to a company’s requirements.

To present and discuss open trace defects uncovered in an FR4 assembly during electrical testing.

This paper presents open trace defects observed in FR4 assemblies and analyses the distribution of defects. The paper also discusses possible root causes for their occurrence.

The open trace defects that occurred during printed circuit board (PCB) fabrication should have been observed by the board manufacturer. It appears that the PCB manufacturer did not perform automatic optical inspection (AOI) and electrical testing during the manufacturing of the boards. The cost due to the rejected PCBAs was approximately 3x times that of the PCB cost.

The paper highlights the costly impact of uncovering a PCB defect after assembly. Based on the results of this study, the implementation of electrical testing and AOI for PCBs is recommended.

The purpose of this paper is to evaluate the reliability of solder joints made on long FR-4 and metal core printed circuit boards using the accelerated thermal cycling.

Solder joints of diodes and resistors samples made on long FR-4 and aluminum (Al) core printed circuit boards were examined. Two kinds of solder pastes were used for the samples preparation. All samples were subjected to temperature aging cycles (−40°C – 3 hours/+85°C – 3 hours). Solder joints resistance, X-Ray inspection and metallographic cross-sections for samples as received and after 100, 500 and 1,000 hours of thermal cycles were utilized for solder joints assessment.

It was stated that 1,000 hours of thermal cycles were enough to show reliability problems in solder joints on long and/or AL core printed circuit board assembly (PCBA). The solder joints of R1206 components were the most sensitive reliability elements. The solder joints of LED diodes are more reliable than solder joints of R1206 resistors. Solder joints made on FR-4 substrate were about two times more reliable than ones on AL core substrate. Cracks in solder joints were the visible reason of solder joints failures.

The influence of thermal cycles on the reliability of solder joints on long, FR-4 and metal core printed circuit boards were presented. Findings from this paper can be used for planning of reliability trials during validation of reflow processes of products containing long or long metal core printed circuit boards (PCBs).

A general introduction is given to surface mounted devices, processes and machinery, followed by Mullard Electronic Assemblies Division's experience and a description of practical assemblies using surface mounted devices. Thoughts of future possibilities and requirements of substrate systems for the advancement of surface mounted assemblies are also presented.

Aims to explain the main requirements for printed circuit boards (PCBs) and to determine the survival rate of boards in lead‐free assembly.

The first two main requirements are the survival of 5‐6 cycles lead free reflow with peak temperatures of up to 260°C and an identical or even better board reliability of such boards compared to todays eutectic soldered ones. In a first series of tests the influence of base materials, reflow temperature gradient and peak temperature on PCB survival rate are investigated. Thermo‐mechanical data of different epoxy‐based materials are compared to survival rate investigations using repeated reflow tests. The impact of PCB manufacturing and design on the lead free performance is discussed. A second series of investigations is air‐to‐air life cycle tests of daisy chain boards out of different epoxy‐based materials with varying preconditioning were done.

The tests showed that dicy cured epoxy base materials are not able to withstand the thermal stress of the mentioned soldering steps. Board design and the heating gradient in reflow also influence the assembly performance. Thermal cycling tests (air‐to‐air), showed clearly the effect of reflow temperature and number of reflow cycles on through‐hole reliability. There was no significant impact of z‐axis‐expansion on the through‐hole failure rate in air‐to‐air cycling.

Provides further information on the lead‐free assembly of PCBs.

THE Vancouver Division of Hewlett‐Packard, Vancouver, Washington, USA, designs and manufactures workstation printers. The evolution of design and manufacturing processes through each product generation has allowed ongoing design improvements, more efficient use of printed circuit board space, a reduction in the number of circuit boards, and robotic assembly within a Just‐in‐Time (JIT) manufacturing environment.

The purpose of this study is to show that the humidity levels for surface insulation resistance (SIR)-related failures are dependent on the type of activators used in no-clean flux systems and to demonstrate the possibility of simulating the effects of humidity and contamination on printed circuit board components and sensitive parts if typical SIR data connected to a particular climatic condition are available. This is shown on representative components and typical circuits.

A range of SIR values obtained on SIR patterns with 1,476 squares was used as input data for the circuit analysis. The SIR data were compared to the surface resistance values observable on a real device printed circuit board assembly. SIR issues at the component and circuit levels were analysed on the basis of parasitic circuit effects owing to the formation of a water layer as an electrical conduction medium.

This paper provides a summary of the effects of contamination with various weak organic acids representing the active components in no-clean solder flux residue, and demonstrates the effect of humidity and contamination on the possible malfunctions and errors in electronic circuits. The effect of contamination and humidity is expressed as drift from the nominal resistance values of the resistors, self-discharge of the capacitors and the errors in the circuits due to parasitic leakage currents (reduction of SIR).

The methodology of the analysis of the circuits using a range of empirical leakage resistance values combined with the knowledge of the humidity and contamination profile of the electronics can be used for the robust design of a device, which is also important for electronic products relying on low current consumption for long battery lifetime.

Examples provide a basic link between the combined effect of humidity and contamination and the performance of electronic circuits. The methodology shown provides the possibility of addressing the climatic reliability of an electronic device at the early stage of device design by using typical SIR data representing the possible climate exposure.

The purpose of this paper is to propose an effective and efficient solution method for the component allocation problem (CAP) in printed circuit board (PCB) assembly, in order to achieve high‐throughput rates of the PCB assembly lines.

The investigated CAP is intertwined with the machine optimization problems for each machine in the line because the latter determine the process time of each machine. In order to solve the CAP, a solution method, which integrates a meta‐heuristic (genetic algorithm) and a regression model is proposed.

It is found that the established regression model can estimate the process time of each machine accurately and efficiently. Experimental tests show that the proposed solution method can solve the CAP both effectively and efficiently.

Although different regression models are required for different types of assembly machines, the proposed solution method can be adopted for solving the CAPs for assembly lines of any configuration, including a mixed‐vendor assembly line.

The solution method can ensure a high‐throughput rate of a PCB assembly line, and thus improve the production capacity without further investment on the expensive PCB assembly equipment.

The paper proposes an innovative solution method for the CAP in PCB assembly. The solution method integrates the meta‐heuristic method and the regression method, which has not been studied in the literature.

A no‐clean mass reflow process for 396‐pin, 324‐pin and 225‐pin over moulded plastic pad array carriers (OMPACs) or plastic ball grid array (BGA) is presented. Emphasis is placed on the OMPAC assembly parameters such as the design, material and process of the packages and printed circuit board (PCB), solder paste, stencil design, printing technology, pick and place, mass re‐flow and inspection. Furthermore, cross‐sections and the ‘popcorn’ effect of the OMPAC assembly are provided and discussed.