Search results

1 – 10 of 14
Article
Publication date: 9 August 2021

Premmilaah Gunasegaran, Jagadheswaran Rajendran, Selvakumar Mariappan, Yusman Mohd Yusof, Zulfiqar Ali Abdul Aziz and Narendra Kumar

The purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while…

Abstract

Purpose

The purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while maintaining a power gain of more than 20 dB for complementary metal oxide semiconductor (CMOS) power amplifier (PA).

Design/methodology/approach

The linearization mechanism is executed with an aid of a passive linearizer implemented at the gate of the main amplifier to minimize the effect of Cgs capacitance through the generation of opposite phase response at the main amplifier. The inductor-less output matching network presents an almost lossless output matching network which contributes to high gain, PAE and output power. The linearity performance is improved without the penalty of power consumption, power gain and stability.

Findings

With this topology, the PA delivers more than 20 dB gain for the Bluetooth Low Energy (BLE) Band from 2.4 GHz to 2.5 GHz with a supply headroom of 1.8 V. At the center frequency of 2.45 GHz, the PA exhibits a gain of 23.3 dB with corresponding peak PAE of 40.11% at a maximum output power of 14.3 dBm. At a maximum linear output power of 12.7 dBm, a PAE of 37.3% has been achieved with a peak third order intermodulation product of 28.04 dBm with a power consumption of 50.58 mW. This corresponds to ACLR of – 20 dBc, thus qualifying the PA to operate for BLE operation.

Practical implications

The proposed technique is able to boost up the efficiency and output power, as well as linearize the PA closer to 1 dB compression point. This reduces the trade-off between linear output power and PAE in CMOS PA design.

Originality/value

The proposed CMOS PA can be integrated comfortably to a BLE transmitter, allowing it to reduce the transceiver’s overall power consumption.

Details

Microelectronics International, vol. 38 no. 2
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 22 February 2021

Selvakumar Mariappan, Jagadheswaran Rajendran, Norlaili Mohd Noh, Yusman Yusof and Narendra Kumar

The purpose of this paper is to implement a highly linear 180 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) to meet the stringent linearity requirement of…

Abstract

Purpose

The purpose of this paper is to implement a highly linear 180 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) to meet the stringent linearity requirement of an long term evolution (LTE) signal with minimum trade-off to power added efficiency (PAE).

Design/methodology/approach

The CMOS PA is designed in a cascaded dual-stage configuration comprises a driver amplifier and a main PA. The gate voltage (VGS) of the driver amplifier is tuned to optimize its positive third-order transconductance (gm3) to be canceled with the main PA’s fixed negative gm3. The gm3 cancellation between these stages mitigates the third-order intermodulation product (IMD3) that contributes to enhanced linearity.

Findings

For driver’s VGS of 0.82 V with continuous wave signal, the proposed PA achieved a power gain of 14.5 dB with a peak PAE of 31.8% and a saturated output power of 23.3 dBm at 2.45 GHz. A maximum third-order output intercept point of 34 dBm is achieved at 20.2 dBm output power with a corresponding IMD3 of −33.4 dBc. When tested with a 20 MHz LTE signal, the PA delivers 19 dBm maximum linear output power for an adjacent channel leakage ratio specification of −30 dBc.

Originality/value

In this study, a novel cascaded gm3 cancellation technique has been implemented to achieve a maximum linear output power under modulated signals.

Details

Circuit World, vol. 48 no. 2
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 31 March 2020

Min Liu, Panpan Xu, Jincan Zhang, Bo Liu and Liwen Zhang

Power amplifiers (PAs) play an important role in wireless communications because they dominate system performance. High-linearity broadband PAs are of great value for potential…

Abstract

Purpose

Power amplifiers (PAs) play an important role in wireless communications because they dominate system performance. High-linearity broadband PAs are of great value for potential use in multi-band system implementation. The purpose of this paper is to present a cascode power amplifier architecture to achieve high power and high efficiency requirements for 4.2∼5.4 GHz applications.

Design/methodology/approach

A common emitter (CE) configuration with a stacked common base configuration of heterojunction bipolar transistor (HBT) is used to achieve high power. T-type matching network is used as input matching network. To increase the bandwidth, the output matching networks are implemented using the two L-networks.

Findings

By using the proposed method, the stacked PA demonstrates a maximum saturated output power of 26.2 dBm, a compact chip size of 1.17 × 0.59 mm2 and a maximum power-added efficiency of 46.3 per cent. The PA shows a wideband small signal gain with less than 3 dB variation over working frequency. The saturated output power of the proposed PA is higher than 25 dBm between 4.2 and 5.4 GHz.

Originality/value

The technology adopted for the design of the 4.2-to-5.4 GHz stacked PA is the 2-µm gallium arsenide HBT process. Based on the proposed method, a better power performance of 3 dB improvement can be achieved as compared with the conventional CE or common-source amplifier because of high output stacking impedance.

Details

Circuit World, vol. 46 no. 4
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 17 September 2020

Mohammad Sadegh Mirzajani Darestani, Mohammad Bagher Tavakoli and Parviz Amiri

The purpose of this paper is to propose a new design strategy to enhance the bandwidth and efficiency of the power amplifier.

Abstract

Purpose

The purpose of this paper is to propose a new design strategy to enhance the bandwidth and efficiency of the power amplifier.

Design/methodology/approach

To realize the introduced design strategy, a power amplifier was designed using TSMC CMOS 0.18um technology for operating in the Ka-band, i.e. the frequency range of 26.5-40 GHz. To design the power amplifier, first, a power divider (PD) with a very wide bandwidth, i.e. 1-40 GHz, was designed to cover the whole Ka-band. The designed Doherty power amplifier consisted of two different amplification paths called main and auxiliary. To amplify the signal in each of the two pathways, a cascade distributed power amplifier was used. The main reason for combining the distributed structure and cascade structure was to increase the gain and linearity of the power amplifier.

Findings

Measurements results for designed power dividers are in good agreement with simulations results. The simulation results for the introduced structure of the power amplifier indicated that the gain of the proposed power amplifier at the frequency of 26-35 GHz was more than 30 dB. The diagram of return loss at the input and output of the power amplifier in the whole Ka-band was less than −8dB. The maximum power-added efficiency (PAE) of the designed power amplifier was 80%. The output P1dB of the introduced structure was 36 dB and the output power of the power amplifier was 36 dBm. Finally, the IP3 value of the power amplifier was about 17 dB.

Originality/value

The strategy presented in this paper is based on the usage of Doherty and distributed structures and a new wideband power divider to benefit from their advantages simultaneously.

Details

Circuit World, vol. 48 no. 1
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 26 January 2010

Amiza Rasmi, Arjuna Marzuki, Mohd Nizam Osman, Ahmad Ismat Abdul Rahim, Mohamed Razman Yahya and Abdul Fatah Awang Mat

The purpose of this paper is to discuss medium‐power amplifier (MPA) design using parasitic‐aware core‐based approach.

Abstract

Purpose

The purpose of this paper is to discuss medium‐power amplifier (MPA) design using parasitic‐aware core‐based approach.

Design/methodology/approach

This paper discusses a core‐based design approach, which can also deliver multi‐band radio frequency integrated circuit.

Findings

A fabricated 3.5 GHz MPA achieved a P1dB of 16.81 dBm, power‐added efficiency (PAE) of 16.74 percent and gain of 6.81 dB at the 10 dBm of input power under a low‐power supply of 3 V. The maximum current, Imax is 80.7 mA and the power consumption of the device is 242.10 mW. A fabricated 2.4 GHz MPA achieved a P1dB of 14.83 dBm, PAE of 11.73 percent and gain of 9.83 dB at the 5.0 dBm of input power under a low‐power supply of 3.0 V. The maximum current, Imax is 84.4 mA and the power consumption for this device is 253.20 mW.

Originality/value

This paper shows the merits of the parasitic‐aware design methods used in designing the core circuit.

Details

Microelectronics International, vol. 27 no. 1
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 9 October 2019

Yanfeng Fang and Yijiang Zhang

This paper aims to implement a new high output power fully integrated 23.1 to 27.2 GHz gallium arsenide heterojunction bipolar transistor power amplifier (PA) to meet the…

Abstract

Purpose

This paper aims to implement a new high output power fully integrated 23.1 to 27.2 GHz gallium arsenide heterojunction bipolar transistor power amplifier (PA) to meet the stringent linearity requirements of LTE systems.

Design/methodology/approach

The direct input power dividing technique is used on the chip. Broadband input and output matching techniques are used for broadband Doherty operation.

Findings

The PA achieves a small-signal gain of 22.8 dB at 25.1 GHz and a saturated output power of 24.3 dBm at 25.1 GHz with a maximum power added efficiency of 31.7%. The PA occupies 1.56 mm2 (including pads) and consumes a maximum current of 79.91 mA from a 9 V supply.

Originality/value

In this paper, the author proposed a novel direct input dividing technique with broadband matching circuits using a low Q output matching technique, and demonstrated a fully-integrated Doherty PA across frequencies of 23.1∼27.2 GHz for long term evolution-license auxiliary access (LTE-LAA) handset applications.

Details

Circuit World, vol. 46 no. 1
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 6 August 2021

Lin-sheng Liu, Qian Lin, Hai-feng Wu, Yi-Jun Chen and Liu-Lin Hu

The design and implementation of a broadband quasi-monolithic microwave integrated circuit (q-MMIC) power amplifier (PA) is presented for 0.2 to 2.2 GHz applications.

Abstract

Purpose

The design and implementation of a broadband quasi-monolithic microwave integrated circuit (q-MMIC) power amplifier (PA) is presented for 0.2 to 2.2 GHz applications.

Design/methodology/approach

To obtain an efficient, high-gain and high-power performance with in a compact and low-cost size, the prototype is based on Gallium nitride (GaN) on SiC 0.25-µm transistors, whereas the passive matching networks are realized on an AlN substrate as thin film circuit.

Findings

Measured results of the q-MMIC PA across the 0.2 to 2.2 GHz band show at least 32 ± 3 dB small-signal gains, an output power of 7 to 12 W and an average power add efficiency greater than 54%. The q-MMIC occupies an area of 12.8 × 14.5 mm2.

Originality/value

To the best of the authors’ knowledge, this work reports the first full integrated PA which covers the frequency range of 0.2 to 2.2 GHz and achieves the combination of highest gain, about 10 W output power, together with the smallest component size among all published GaN PAs to date.

Details

Circuit World, vol. 49 no. 2
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 7 August 2017

Qian Lin, Haifeng Wu and Xi Li

The purpose of this paper is to investigate the temperature reliability for a parallel high-efficiency class-E power amplifier (PA).

Abstract

Purpose

The purpose of this paper is to investigate the temperature reliability for a parallel high-efficiency class-E power amplifier (PA).

Design/methodology/approach

To explore the relationship between temperature and direct current (DC) characteristics, output power, S parameters and efficiency of the PA quantitatively, a series of reliability experiments have been designed and conducted to study the temperature reliability for this PA.

Findings

From the results, the prominent performance degradation even failure is found during the testing. Furthermore, the thermal shock test can cause permanent failure, which is a great threat for PA.

Research limitations/implications

Therefore, to ensure the good performance, the influence of temperature on PA reliability should be carefully considered during the stage of PA design.

Practical implications

All these can provide important guidance for the reliability design of PA.

Social implications

All these can give some important guidance for PA application.

Originality/value

In addition, PA is usually designed according to the electrical properties at the room temperature. From the results above, it can be concluded that it may be unable to satisfy the performance requirement at high temperature. In turn, if it is designed according to the electrical properties at low temperature, the transistor often works in the super-saturated state, the reliability of PA will become the new problem. Therefore, to ensure the good performance, the influence of temperature on PA reliability should be carefully considered during the design.

Details

Circuit World, vol. 43 no. 3
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 27 March 2020

George-Konstantinos Gaitanakis, George Limnaios and Konstantinos Zikidis

Modern fighter aircraft using active electronically scanned array (AESA) fire control radars are able to detect and track targets at long ranges, in the order of 50 nautical miles…

Abstract

Purpose

Modern fighter aircraft using active electronically scanned array (AESA) fire control radars are able to detect and track targets at long ranges, in the order of 50 nautical miles or more. Low observable or stealth technology has contested the radar capabilities, reducing detection/tracking ranges roughly to one-third (or even less, for fighter aircraft radar). Hence, infrared search and track (IRST) systems have been reconsidered as an alternative to the radar. This study aims to explore and compare the capabilities and limitations of these two technologies, AESA radars and IRST systems, as well as their synergy through sensor fusion.

Design/methodology/approach

The AESA radar range is calculated with the help of the radar equation under certain assumptions, taking into account heat dissipation requirements, using the F-16 fighter as a case study. Concerning the IRST sensor, a new model is proposed for the estimation of the detection range, based on the emitted infrared radiation caused by aerodynamic heating.

Findings

The maximum detection range provided by an AESA radar could be restricted because of the increased waste heat which is produced and the relevant constraints concerning the cooling capacity of the carrying aircraft. On the other hand, IRST systems exhibit certain advantages over radars against low observable threats. IRST could be combined with a datalink with the help of data fusion, offering weapons-quality track.

Originality/value

An original approach is provided for the IRST detection range estimation. The AESA/IRST comparison offers valuable insight, while it allows for more efficient planning, at the military acquisition phase, as well as at the tactical level.

Details

Aircraft Engineering and Aerospace Technology, vol. 92 no. 9
Type: Research Article
ISSN: 1748-8842

Keywords

Article
Publication date: 1 March 1989

J.R. Tyler and D.K. Andrade

Recent developments in microwave GaAs technology are yielding devices with higher power capabilities and increased levels of integration. The mechanical and thermal properties of…

Abstract

Recent developments in microwave GaAs technology are yielding devices with higher power capabilities and increased levels of integration. The mechanical and thermal properties of GaAs and other microwave materials play a key role in the design and assembly of microwave power circuits. Thermal management is a critical element of microwave power circuit design. Thermal properties of microwave materials are discussed and compared with standard microelectronic materials. Material selection criteria are described. Assembly and packaging techniques also affect the overall performance of the GaAs power circuit. The high operating frequencies of microwave circuits make ordinary circuit elements, such as wire bonds and printed conductors, reactive. In addition, electrical performance criteria, such as high current or low impedance, create unique assembly demands. The successful development of a GaAs‐based microwave product is dependent on careful attention to the material properties and precise assembly methods. Techniques of automated assembly and processing are discussed, with ah eye towards maintaining high quality and reliability.

Details

Microelectronics International, vol. 6 no. 3
Type: Research Article
ISSN: 1356-5362

1 – 10 of 14